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[ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR instructions.

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The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214498 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller 2014-08-01 11:08:51 +00:00
parent 5e2214cca6
commit 70c9be77f7
2 changed files with 30 additions and 0 deletions
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13
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5747,6 +5747,19 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
"source register and base register can't be identical");
return false;
}
case ARM::LDR_PRE_IMM:
case ARM::LDR_PRE_REG:
case ARM::LDR_POST_IMM:
case ARM::LDR_POST_REG: {
// Rt must be different from Rn.
const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
if (Rt == Rn)
return Error(Operands[3]->getStartLoc(),
"destination register and base register can't be identical");
return false;
}
case ARM::SBFX:
case ARM::UBFX: {
// Width must be in range [1, 32-lsb].

17
test/MC/ARM/diagnostics.s
View File

@ -540,3 +540,20 @@ foo2:
@ CHECK-ERRORS: error: source register and base register can't be identical
@ CHECK-ERRORS: strb r0, [r0], r1
@ CHECK-ERRORS: ^
ldr r0, [r0, #4]!
ldr r0, [r0, r1]!
ldr r0, [r0], #4
ldr r0, [r0], r1
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, #4]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0, r1]!
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0], #4
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldr r0, [r0], r1
@ CHECK-ERRORS: ^