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In LowerEXTRACT_VECTOR_ELT, force an i32 value type for PEXTWR instead of

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incrementing the simple value type of the 16-bit type, which would give the
wrong type if an intemediate MVT (such as i24) were introduced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91602 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ken Dyck 2009-12-17 15:31:52 +00:00
parent 04149f7ffd
commit 70d0ef1459
1 changed files with 1 additions and 1 deletions
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2
lib/Target/X86/X86ISelLowering.cpp
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@ -4584,7 +4584,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
MVT::v4i32, Vec),
Op.getOperand(1)));
// Transform it so it match pextrw which produces a 32-bit result.
EVT EltVT = (MVT::SimpleValueType)(VT.getSimpleVT().SimpleTy+1);
EVT EltVT = MVT::i32;
SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
Op.getOperand(0), Op.getOperand(1));
SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,