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[Hexagon] Removing TFR_condset_ir/TFR_condset_ri modeling.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231689 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-03-09 19:31:25 +00:00
parent 99101c7ca6
commit 70d77d1edc
4 changed files with 0 additions and 64 deletions
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16
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -4727,22 +4727,6 @@ def Y4_trace: CRInst <(outs), (ins IntRegs:$Rs),
let Inst{20-16} = Rs;
}
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3),
"Error; should not emit",
[(set (i32 IntRegs:$dst),
(i32 (select (i1 PredRegs:$src1), (i32 IntRegs:$src2),
s12ImmPred:$src3)))]>;
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3),
"Error; should not emit",
[(set (i32 IntRegs:$dst),
(i32 (select (i1 PredRegs:$src1), s12ImmPred:$src2,
(i32 IntRegs:$src3))))]>;
let AddedComplexity = 100, isPredicated = 1, isCodeGenOnly = 1 in
def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst),
(ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3),

2
lib/Target/Hexagon/HexagonNewValueJump.cpp
View File

@ -200,8 +200,6 @@ static bool commonChecksToProhibitNewValueJump(bool afterRA,
// we don't know the scope of usage and definitions of these
// instructions.
if (MII->getOpcode() == Hexagon::TFR_condset_ii ||
MII->getOpcode() == Hexagon::TFR_condset_ri ||
MII->getOpcode() == Hexagon::TFR_condset_ir ||
MII->getOpcode() == Hexagon::LDriw_pred ||
MII->getOpcode() == Hexagon::STriw_pred)
return false;

6
lib/Target/Hexagon/HexagonPeephole.cpp
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@ -274,12 +274,6 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
case Hexagon::TFR_condset_ii:
NewOp = Op;
break;
case Hexagon::TFR_condset_ri:
NewOp = Hexagon::TFR_condset_ir;
break;
case Hexagon::TFR_condset_ir:
NewOp = Hexagon::TFR_condset_ri;
break;
case Hexagon::C2_muxri:
NewOp = Hexagon::C2_muxir;
break;

40
lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
View File

@ -87,46 +87,6 @@ bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
++MII) {
MachineInstr *MI = MII;
switch(MI->getOpcode()) {
case Hexagon::TFR_condset_ri: {
int DestReg = MI->getOperand(0).getReg();
int SrcReg1 = MI->getOperand(2).getReg();
// Do not emit the predicated copy if the source and the destination
// is the same register.
if (DestReg != SrcReg1) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::A2_tfrt), DestReg).
addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
}
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::C2_cmoveif), DestReg).
addReg(MI->getOperand(1).getReg()).
addImm(MI->getOperand(3).getImm());
MII = MBB->erase(MI);
--MII;
break;
}
case Hexagon::TFR_condset_ir: {
int DestReg = MI->getOperand(0).getReg();
int SrcReg2 = MI->getOperand(3).getReg();
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::C2_cmoveit), DestReg).
addReg(MI->getOperand(1).getReg()).
addImm(MI->getOperand(2).getImm());
// Do not emit the predicated copy if the source and
// the destination is the same register.
if (DestReg != SrcReg2) {
BuildMI(*MBB, MII, MI->getDebugLoc(),
TII->get(Hexagon::A2_tfrf), DestReg).
addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
}
MII = MBB->erase(MI);
--MII;
break;
}
case Hexagon::TFR_condset_ii: {
int DestReg = MI->getOperand(0).getReg();
int SrcReg1 = MI->getOperand(1).getReg();