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Add an explanatory message for an assertion.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123042 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-01-07 23:40:46 +00:00
parent 697970286a
commit 70f85730b1
1 changed files with 2 additions and 1 deletions
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lib/Target/ARM/ARMISelLowering.cpp
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@ -3715,7 +3715,8 @@ SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, SelectionDAG &DAG) con
// Since only 64-bit and 128-bit vectors are legal on ARM and // Since only 64-bit and 128-bit vectors are legal on ARM and
// we've eliminated the other cases... // we've eliminated the other cases...
assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts); assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
"unexpected vector sizes in ReconstructShuffle");
if (MaxElts[i] - MinElts[i] >= NumElts) { if (MaxElts[i] - MinElts[i] >= NumElts) {
// Span too large for a VEXT to cope // Span too large for a VEXT to cope