6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-13 04:30:23 +00:00
Code Issues Projects Releases Wiki Activity

Add AVX SSE3 packed addsub instructions

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-07-01 17:08:18 +00:00
parent 194db3587c
commit 7144821c61
3 changed files with 66 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

57
lib/Target/X86/X86InstrSSE.td
View File

@ -3237,33 +3237,44 @@ def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
} }
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE3 Instructions // SSE3 - Arithmetic
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// Arithmetic multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, bit Is2Addr = 1> {
let Constraints = "$src1 = $dst" in { def rr : I<0xD0, MRMSrcReg,
def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2), !if(Is2Addr,
"addsubps\t{$src2, $dst|$dst, $src2}", !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
VR128:$src2))]>; [(set VR128:$dst, (Int VR128:$src1,
def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem, VR128:$src2))]>;
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2), def rm : I<0xD0, MRMSrcMem,
"addsubps\t{$src2, $dst|$dst, $src2}", (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
[(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1, !if(Is2Addr,
(memop addr:$src2)))]>; !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
def ADDSUBPDrr : S3I<0xD0, MRMSrcReg, !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2), [(set VR128:$dst, (Int VR128:$src1,
"addsubpd\t{$src2, $dst|$dst, $src2}", (memop addr:$src2)))]>;
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
VR128:$src2))]>;
def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
(outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
"addsubpd\t{$src2, $dst|$dst, $src2}",
[(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
(memop addr:$src2)))]>;
} }
let isAsmParserOnly = 1, Predicates = [HasSSE3, HasAVX],
ExeDomain = SSEPackedDouble in {
defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", 0>, XD,
VEX_4V;
defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", 0>, OpSize,
VEX_4V;
}
let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
ExeDomain = SSEPackedDouble in {
defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps">, XD;
defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd">, TB, OpSize;
}
//===---------------------------------------------------------------------===//
// SSE3 Instructions
//===---------------------------------------------------------------------===//
def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
"lddqu\t{$src, $dst|$dst, $src}", "lddqu\t{$src, $dst|$dst, $src}",
[(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>; [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;

16
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -11566,3 +11566,19 @@
// CHECK: encoding: [0xc5,0xfb,0x12,0x10] // CHECK: encoding: [0xc5,0xfb,0x12,0x10]
vmovddup (%eax), %xmm2 vmovddup (%eax), %xmm2
// CHECK: vaddsubps %xmm1, %xmm2, %xmm3
// CHECK: encoding: [0xc5,0xeb,0xd0,0xd9]
vaddsubps %xmm1, %xmm2, %xmm3
// CHECK: vaddsubps (%eax), %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xf3,0xd0,0x10]
vaddsubps (%eax), %xmm1, %xmm2
// CHECK: vaddsubpd %xmm1, %xmm2, %xmm3
// CHECK: encoding: [0xc5,0xe9,0xd0,0xd9]
vaddsubpd %xmm1, %xmm2, %xmm3
// CHECK: vaddsubpd (%eax), %xmm1, %xmm2
// CHECK: encoding: [0xc5,0xf1,0xd0,0x10]
vaddsubpd (%eax), %xmm1, %xmm2

16
test/MC/AsmParser/X86/x86_64-encoding.s
View File

@ -1614,3 +1614,19 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: encoding: [0xc5,0x7b,0x12,0x20] // CHECK: encoding: [0xc5,0x7b,0x12,0x20]
vmovddup (%rax), %xmm12 vmovddup (%rax), %xmm12
// CHECK: vaddsubps %xmm11, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x41,0x1b,0xd0,0xeb]
vaddsubps %xmm11, %xmm12, %xmm13
// CHECK: vaddsubps (%rax), %xmm11, %xmm12
// CHECK: encoding: [0xc5,0x23,0xd0,0x20]
vaddsubps (%rax), %xmm11, %xmm12
// CHECK: vaddsubpd %xmm11, %xmm12, %xmm13
// CHECK: encoding: [0xc4,0x41,0x19,0xd0,0xeb]
vaddsubpd %xmm11, %xmm12, %xmm13
// CHECK: vaddsubpd (%rax), %xmm11, %xmm12
// CHECK: encoding: [0xc5,0x21,0xd0,0x20]
vaddsubpd (%rax), %xmm11, %xmm12