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Promotion of sdiv/srem/udiv/urem.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2007-10-31 08:57:43 +00:00
parent 1bd3271b16
commit 7169a2f9e8
1 changed files with 32 additions and 0 deletions
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32
lib/CodeGen/SelectionDAG/LegalizeDAGTypes.cpp
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@ -147,6 +147,8 @@ private:
SDOperand PromoteResult_SETCC(SDNode *N);
SDOperand PromoteResult_LOAD(LoadSDNode *N);
SDOperand PromoteResult_SimpleIntBinOp(SDNode *N);
SDOperand PromoteResult_SDIV(SDNode *N);
SDOperand PromoteResult_UDIV(SDNode *N);
SDOperand PromoteResult_SHL(SDNode *N);
SDOperand PromoteResult_SRA(SDNode *N);
SDOperand PromoteResult_SRL(SDNode *N);
@ -554,6 +556,12 @@ void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
case ISD::SUB:
case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
case ISD::SDIV:
case ISD::SREM: Result = PromoteResult_SDIV(N); break;
case ISD::UDIV:
case ISD::UREM: Result = PromoteResult_UDIV(N); break;
case ISD::SHL: Result = PromoteResult_SHL(N); break;
case ISD::SRA: Result = PromoteResult_SRA(N); break;
case ISD::SRL: Result = PromoteResult_SRL(N); break;
@ -694,6 +702,30 @@ SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
// Sign extend the input.
SDOperand LHS = GetPromotedOp(N->getOperand(0));
SDOperand RHS = GetPromotedOp(N->getOperand(1));
MVT::ValueType VT = N->getValueType(0);
LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
DAG.getValueType(VT));
RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
DAG.getValueType(VT));
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
// Zero extend the input.
SDOperand LHS = GetPromotedOp(N->getOperand(0));
SDOperand RHS = GetPromotedOp(N->getOperand(1));
MVT::ValueType VT = N->getValueType(0);
LHS = DAG.getZeroExtendInReg(LHS, VT);
RHS = DAG.getZeroExtendInReg(RHS, VT);
return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
}
SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
GetPromotedOp(N->getOperand(0)), N->getOperand(1));