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Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
fffc0fe42c
commit
717cdb0df8
@ -1629,3 +1629,37 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty,
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llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// BMI
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_bmi_bextr_32 : GCCBuiltin<"__builtin_ia32_bextr_u32">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_bextr_64 : GCCBuiltin<"__builtin_ia32_bextr_u64">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_bzhi_32 : GCCBuiltin<"__builtin_ia32_bzhi_si">,
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_bzhi_64 : GCCBuiltin<"__builtin_ia32_bzhi_di">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_blsi_32 :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_blsi_64 :
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_blsmsk_32 :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_blsmsk_64 :
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_blsr_32 :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_blsr_64 :
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_pdep_32 :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_pdep_64 :
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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def int_x86_bmi_pext_32 :
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Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_x86_bmi_pext_64 :
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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}
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@ -1401,57 +1401,80 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
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}
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multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,
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RegisterClass RC, X86MemOperand x86memop> {
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RegisterClass RC, X86MemOperand x86memop, Intrinsic Int,
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PatFrag ld_frag> {
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def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (Int RC:$src)), (implicit EFLAGS)]>, T8, VEX_4V;
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def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, T8, VEX_4V;
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!strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (Int (ld_frag addr:$src))), (implicit EFLAGS)]>,
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T8, VEX_4V;
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}
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>;
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defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W;
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defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>;
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defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W;
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defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>;
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defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W;
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defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem,
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int_x86_bmi_blsr_32, loadi32>;
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defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem,
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int_x86_bmi_blsr_64, loadi64>, VEX_W;
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defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem,
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int_x86_bmi_blsmsk_32, loadi32>;
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defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem,
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int_x86_bmi_blsmsk_64, loadi64>, VEX_W;
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defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem,
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int_x86_bmi_blsi_32, loadi32>;
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defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem,
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int_x86_bmi_blsi_64, loadi64>, VEX_W;
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}
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multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC,
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X86MemOperand x86memop> {
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X86MemOperand x86memop, Intrinsic Int,
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PatFrag ld_frag> {
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def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, T8, VEX_4VOp3;
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[(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
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T8, VEX_4VOp3;
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def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, T8, VEX_4VOp3;
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[(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
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(implicit EFLAGS)]>, T8, VEX_4VOp3;
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}
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let Predicates = [HasBMI], Defs = [EFLAGS] in {
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defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem>;
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defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem>, VEX_W;
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defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem,
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int_x86_bmi_bextr_32, loadi32>;
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defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem,
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int_x86_bmi_bextr_64, loadi64>, VEX_W;
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}
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let Predicates = [HasBMI2], Defs = [EFLAGS] in {
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defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem>;
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defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem>, VEX_W;
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defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem,
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int_x86_bmi_bzhi_32, loadi32>;
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defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem,
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int_x86_bmi_bzhi_64, loadi64>, VEX_W;
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}
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multiclass bmi_pdep_pextr<string mnemonic, RegisterClass RC,
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X86MemOperand x86memop> {
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multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
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X86MemOperand x86memop, Intrinsic Int,
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PatFrag ld_frag> {
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def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V;
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[(set RC:$dst, (Int RC:$src1, RC:$src2))]>,
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VEX_4V;
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def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
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!strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[]>, VEX_4V;
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[(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
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}
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let Predicates = [HasBMI2] in {
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defm PDEP32 : bmi_pdep_pextr<"pdep{l}", GR32, i32mem>, T8XD;
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defm PDEP64 : bmi_pdep_pextr<"pdep{q}", GR64, i64mem>, T8XD, VEX_W;
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defm PEXTR32 : bmi_pdep_pextr<"pextr{l}", GR32, i32mem>, T8XS;
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defm PEXTR64 : bmi_pdep_pextr<"pextr{q}", GR64, i64mem>, T8XS, VEX_W;
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defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem,
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int_x86_bmi_pdep_32, loadi32>, T8XD;
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defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem,
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int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W;
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defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem,
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int_x86_bmi_pext_32, loadi32>, T8XS;
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defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem,
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int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W;
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}
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//===----------------------------------------------------------------------===//
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@ -1,4 +1,4 @@
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; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mattr=+bmi,+bmi2 | FileCheck %s
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define i32 @t1(i32 %x) nounwind {
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%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
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@ -51,3 +51,130 @@ define i64 @andn64(i64 %x, i64 %y) nounwind readnone {
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; CHECK: andn64:
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; CHECK: andnq
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}
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define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: bextr32:
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; CHECK: bextrl
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}
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declare i32 @llvm.x86.bmi.bextr.32(i32, i32) nounwind readnone
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define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: bextr64:
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; CHECK: bextrq
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}
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declare i64 @llvm.x86.bmi.bextr.64(i64, i64) nounwind readnone
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define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: bzhi32:
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; CHECK: bzhil
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}
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declare i32 @llvm.x86.bmi.bzhi.32(i32, i32) nounwind readnone
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define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: bzhi64:
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; CHECK: bzhiq
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}
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declare i64 @llvm.x86.bmi.bzhi.64(i64, i64) nounwind readnone
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define i32 @blsi32(i32 %x) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.blsi.32(i32 %x)
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ret i32 %tmp
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; CHECK: blsi32:
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; CHECK: blsil
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}
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declare i32 @llvm.x86.bmi.blsi.32(i32) nounwind readnone
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define i64 @blsi64(i64 %x) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.blsi.64(i64 %x)
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ret i64 %tmp
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; CHECK: blsi64:
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; CHECK: blsiq
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}
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declare i64 @llvm.x86.bmi.blsi.64(i64) nounwind readnone
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define i32 @blsmsk32(i32 %x) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.blsmsk.32(i32 %x)
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ret i32 %tmp
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; CHECK: blsmsk32:
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; CHECK: blsmskl
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}
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declare i32 @llvm.x86.bmi.blsmsk.32(i32) nounwind readnone
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define i64 @blsmsk64(i64 %x) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.blsmsk.64(i64 %x)
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ret i64 %tmp
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; CHECK: blsmsk64:
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; CHECK: blsmskq
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}
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declare i64 @llvm.x86.bmi.blsmsk.64(i64) nounwind readnone
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define i32 @blsr32(i32 %x) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.blsr.32(i32 %x)
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ret i32 %tmp
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; CHECK: blsr32:
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; CHECK: blsrl
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}
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declare i32 @llvm.x86.bmi.blsr.32(i32) nounwind readnone
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define i64 @blsr64(i64 %x) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.blsr.64(i64 %x)
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ret i64 %tmp
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; CHECK: blsr64:
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; CHECK: blsrq
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}
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declare i64 @llvm.x86.bmi.blsr.64(i64) nounwind readnone
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define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: pdep32:
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; CHECK: pdepl
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}
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declare i32 @llvm.x86.bmi.pdep.32(i32, i32) nounwind readnone
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define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: pdep64:
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; CHECK: pdepq
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}
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declare i64 @llvm.x86.bmi.pdep.64(i64, i64) nounwind readnone
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define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
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%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
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ret i32 %tmp
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; CHECK: pext32:
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; CHECK: pextl
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}
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declare i32 @llvm.x86.bmi.pext.32(i32, i32) nounwind readnone
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define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
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%tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
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ret i64 %tmp
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; CHECK: pext64:
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; CHECK: pextq
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}
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declare i64 @llvm.x86.bmi.pext.64(i64, i64) nounwind readnone
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@ -564,16 +564,16 @@
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# CHECK: bzhiq %r12, %r11, %r10
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0xc4 0x42 0x98 0xf5 0xd3
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# CHECK: pextrl %r12d, %r11d, %r10d
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# CHECK: pextl %r12d, %r11d, %r10d
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0xc4 0x42 0x22 0xf5 0xd4
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# CHECK: pextrl (%rax), %r11d, %r10d
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# CHECK: pextl (%rax), %r11d, %r10d
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0xc4 0x62 0x22 0xf5 0x10
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# CHECK: pextrq %r12, %r11, %r10
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# CHECK: pextq %r12, %r11, %r10
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0xc4 0x42 0xa2 0xf5 0xd4
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# CHECK: pextrq (%rax), %r11, %r10
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# CHECK: pextq (%rax), %r11, %r10
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0xc4 0x62 0xa2 0xf5 0x10
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# CHECK: pdepl %r12d, %r11d, %r10d
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@ -520,10 +520,10 @@
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# CHECK: bzhil %esi, %ebx, %edx
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0xc4 0xe2 0x08 0xf5 0xd3
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# CHECK: pextrl %esp, %ecx, %edx
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# CHECK: pextl %esp, %ecx, %edx
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0xc4 0xe2 0x72 0xf5 0xd4
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# CHECK: pextrl (%eax), %ecx, %edx
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# CHECK: pextl (%eax), %ecx, %edx
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0xc4 0xe2 0x72 0xf5 0x10
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# CHECK: pdepl %esp, %ecx, %edx
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@ -88,21 +88,21 @@
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// CHECK: encoding: [0xc4,0x42,0x98,0xf5,0xd3]
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bzhiq %r12, %r11, %r10
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// CHECK: pextrl %r12d, %r11d, %r10d
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// CHECK: pextl %r12d, %r11d, %r10d
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// CHECK: encoding: [0xc4,0x42,0x22,0xf5,0xd4]
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pextrl %r12d, %r11d, %r10d
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pextl %r12d, %r11d, %r10d
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// CHECK: pextrl (%rax), %r11d, %r10d
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// CHECK: pextl (%rax), %r11d, %r10d
|
||||
// CHECK: encoding: [0xc4,0x62,0x22,0xf5,0x10]
|
||||
pextrl (%rax), %r11d, %r10d
|
||||
pextl (%rax), %r11d, %r10d
|
||||
|
||||
// CHECK: pextrq %r12, %r11, %r10
|
||||
// CHECK: pextq %r12, %r11, %r10
|
||||
// CHECK: encoding: [0xc4,0x42,0xa2,0xf5,0xd4]
|
||||
pextrq %r12, %r11, %r10
|
||||
pextq %r12, %r11, %r10
|
||||
|
||||
// CHECK: pextrq (%rax), %r11, %r10
|
||||
// CHECK: pextq (%rax), %r11, %r10
|
||||
// CHECK: encoding: [0xc4,0x62,0xa2,0xf5,0x10]
|
||||
pextrq (%rax), %r11, %r10
|
||||
pextq (%rax), %r11, %r10
|
||||
|
||||
// CHECK: pdepl %r12d, %r11d, %r10d
|
||||
// CHECK: encoding: [0xc4,0x42,0x23,0xf5,0xd4]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user