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https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Changes in operations on masks registers for KNL and SKX
- Added KSHIFTB/D/Q for skx - Added KORTESTB/D/Q for skx - Fixed store operation for v8i1 type for KNL - Store size of v8i1, v4i1 and v2i1 are changed to 8 bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227043 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
c4fbd5d26b
commit
717d41d8c3
@ -12871,6 +12871,8 @@ X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const
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MVT EltVT = Op.getSimpleValueType();
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assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
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assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
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"Unexpected vector type in ExtractBitFromMaskVector");
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// variable index can't be handled in mask registers,
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// extend vector to VR512
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@ -12884,6 +12886,8 @@ X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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const TargetRegisterClass* rc = getRegClassFor(VecVT);
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if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
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rc = getRegClassFor(MVT::v16i1);
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unsigned MaxSift = rc->getSize()*8 - 1;
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Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
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DAG.getConstant(MaxSift - IdxVal, MVT::i8));
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@ -1624,7 +1624,8 @@ multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
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[(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
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let mayStore = 1 in
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def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(store KRC:$src, addr:$dst)]>;
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}
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}
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@ -1951,13 +1952,26 @@ multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
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multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
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defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
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VEX, PS;
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let Predicates = [HasDQI] in
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defm B : avx512_mask_testop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
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VEX, PD;
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let Predicates = [HasBWI] in {
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defm Q : avx512_mask_testop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
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VEX, PS, VEX_W;
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defm D : avx512_mask_testop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
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VEX, PD, VEX_W;
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}
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}
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defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
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def : Pat<(X86cmp VK1:$src1, (i1 0)),
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(KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
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(COPY_TO_REGCLASS VK1:$src1, VK16))>;
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(COPY_TO_REGCLASS VK1:$src1, VK16))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(X86cmp VK1:$src1, (i1 0)),
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(KORTESTBrr (COPY_TO_REGCLASS VK1:$src1, VK8),
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(COPY_TO_REGCLASS VK1:$src1, VK8))>, Requires<[HasDQI]>;
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// Mask shift
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multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
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@ -1972,7 +1986,17 @@ multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
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multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
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SDNode OpNode> {
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defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
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VEX, TAPD, VEX_W;
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VEX, TAPD, VEX_W;
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let Predicates = [HasDQI] in
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defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
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VEX, TAPD;
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let Predicates = [HasBWI] in {
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defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
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VEX, TAPD, VEX_W;
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let Predicates = [HasDQI] in
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defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
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VEX, TAPD;
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}
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}
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defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
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@ -2023,10 +2047,14 @@ let Predicates = [HasVLX] in {
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}
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def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
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(v8i1 (COPY_TO_REGCLASS
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(KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16),
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(I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
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(v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
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(v8i1 (COPY_TO_REGCLASS
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(KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16),
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(I8Imm $imm)), VK8))>, Requires<[HasAVX512, NoDQI]>;
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//===----------------------------------------------------------------------===//
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// AVX-512 - Aligned and unaligned load and store
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//
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@ -5204,7 +5232,14 @@ def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
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def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
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def : Pat<(store VK1:$src, addr:$dst),
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(KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)),
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sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
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def : Pat<(store VK8:$src, addr:$dst),
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(MOV8mr addr:$dst,
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(EXTRACT_SUBREG (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
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sub_8bit))>, Requires<[HasAVX512, NoDQI]>;
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def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
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(truncstore node:$val, node:$ptr), [{
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@ -469,18 +469,18 @@ def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
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256, (sequence "YMM%u", 0, 31)>;
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// Mask registers
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def VK1 : RegisterClass<"X86", [i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
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def VK2 : RegisterClass<"X86", [v2i1], 16, (add VK1)> {let Size = 16;}
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def VK4 : RegisterClass<"X86", [v4i1], 16, (add VK2)> {let Size = 16;}
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def VK8 : RegisterClass<"X86", [v8i1], 16, (add VK4)> {let Size = 16;}
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def VK1 : RegisterClass<"X86", [i1], 8, (sequence "K%u", 0, 7)> {let Size = 8;}
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def VK2 : RegisterClass<"X86", [v2i1], 8, (add VK1)> {let Size = 8;}
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def VK4 : RegisterClass<"X86", [v4i1], 8, (add VK2)> {let Size = 8;}
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def VK8 : RegisterClass<"X86", [v8i1], 8, (add VK4)> {let Size = 8;}
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def VK16 : RegisterClass<"X86", [v16i1], 16, (add VK8)> {let Size = 16;}
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def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
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def VK64 : RegisterClass<"X86", [v64i1], 64, (add VK32)> {let Size = 64;}
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def VK1WM : RegisterClass<"X86", [i1], 16, (sub VK1, K0)> {let Size = 16;}
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def VK2WM : RegisterClass<"X86", [v2i1], 16, (sub VK2, K0)> {let Size = 16;}
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def VK4WM : RegisterClass<"X86", [v4i1], 16, (sub VK4, K0)> {let Size = 16;}
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def VK8WM : RegisterClass<"X86", [v8i1], 16, (sub VK8, K0)> {let Size = 16;}
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def VK1WM : RegisterClass<"X86", [i1], 8, (sub VK1, K0)> {let Size = 8;}
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def VK2WM : RegisterClass<"X86", [v2i1], 8, (sub VK2, K0)> {let Size = 8;}
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def VK4WM : RegisterClass<"X86", [v4i1], 8, (sub VK4, K0)> {let Size = 8;}
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def VK8WM : RegisterClass<"X86", [v8i1], 8, (sub VK8, K0)> {let Size = 8;}
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def VK16WM : RegisterClass<"X86", [v16i1], 16, (add VK8WM)> {let Size = 16;}
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def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
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def VK64WM : RegisterClass<"X86", [v64i1], 64, (add VK32WM)> {let Size = 64;}
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@ -106,7 +106,8 @@ define i32 @test10(<16 x i32> %x, i32 %ind) nounwind {
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;CHECK: vpcmpltud
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;CHECK: kshiftlw $11
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;KNL: kortestw
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;SKX: kortestb
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;CHECK: je
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;CHECK: ret
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;CHECK: ret
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@ -125,7 +126,8 @@ define <16 x i32> @test11(<16 x i32>%a, <16 x i32>%b) {
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;CHECK: vpcmpgtq
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;CHECK: kshiftlw $15
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;KNL: kortestw
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;SKX: kortestb
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;CHECK: ret
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define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
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@ -150,9 +152,12 @@ define i16 @test13(i32 %a, i32 %b) {
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;CHECK-LABEL: test14
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;CHECK: vpcmpgtq
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;CHECK: kshiftlw $11
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;CHECK: kshiftrw $15
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;CHECK: kortestw
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;KNL: kshiftlw $11
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;KNL: kshiftrw $15
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;KNL: kortestw
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;SKX: kshiftlb $3
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;SKX: kshiftrb $7
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;SKX: kortestb
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;CHECK: ret
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define i64 @test14(<8 x i64>%a, <8 x i64>%b, i64 %a1, i64 %b1) {
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@ -188,9 +193,11 @@ define i16 @test16(i1 *%addr, i16 %a) {
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}
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;CHECK-LABEL: test17
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;CHECK: kshiftlw
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;CHECK: kshiftrw
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;KNL: kshiftlw
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;KNL: kshiftrw
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;KNL: korw
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;SKX: kshiftlb
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;SKX: kshiftrb
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;SKX: korb
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;CHECK: ret
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define i8 @test17(i1 *%addr, i8 %a) {
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@ -1,29 +1,38 @@
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=KNL --check-prefix=CHECK
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=SKX --check-prefix=CHECK
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; CHECK-LABEL: mask16
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; CHECK: kmovw
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw
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define i16 @mask16(i16 %x) {
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%m0 = bitcast i16 %x to <16 x i1>
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%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <16 x i1> %m1 to i16
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ret i16 %ret
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; CHECK-LABEL: mask16
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; CHECK: kmovw
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw
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; CHECK: ret
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}
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; CHECK-LABEL: mask8
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; KNL: kmovw
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; KNL-NEXT: knotw
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; KNL-NEXT: kmovw
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; SKX: kmovb
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; SKX-NEXT: knotb
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; SKX-NEXT: kmovb
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define i8 @mask8(i8 %x) {
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%m0 = bitcast i8 %x to <8 x i1>
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%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <8 x i1> %m1 to i8
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ret i8 %ret
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; CHECK-LABEL: mask8
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; CHECK: kmovw
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw
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; CHECK: ret
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}
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; CHECK-LABEL: mask16_mem
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; CHECK: kmovw ([[ARG1:%rdi|%rcx]]), %k{{[0-7]}}
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
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; CHECK: ret
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define void @mask16_mem(i16* %ptr) {
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%x = load i16* %ptr, align 4
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%m0 = bitcast i16 %x to <16 x i1>
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@ -31,13 +40,16 @@ define void @mask16_mem(i16* %ptr) {
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%ret = bitcast <16 x i1> %m1 to i16
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store i16 %ret, i16* %ptr, align 4
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ret void
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; CHECK-LABEL: mask16_mem
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; CHECK: kmovw ([[ARG1:%rdi|%rcx]]), %k{{[0-7]}}
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
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; CHECK: ret
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}
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; CHECK-LABEL: mask8_mem
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; KNL: kmovw ([[ARG1]]), %k{{[0-7]}}
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; KNL-NEXT: knotw
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; KNL-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
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; SKX: kmovb ([[ARG1]]), %k{{[0-7]}}
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; SKX-NEXT: knotb
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; SKX-NEXT: kmovb %k{{[0-7]}}, ([[ARG1]])
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define void @mask8_mem(i8* %ptr) {
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%x = load i8* %ptr, align 4
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%m0 = bitcast i8 %x to <8 x i1>
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@ -45,13 +57,12 @@ define void @mask8_mem(i8* %ptr) {
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%ret = bitcast <8 x i1> %m1 to i8
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store i8 %ret, i8* %ptr, align 4
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ret void
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; CHECK-LABEL: mask8_mem
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; CHECK: kmovw ([[ARG1]]), %k{{[0-7]}}
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw %k{{[0-7]}}, ([[ARG1]])
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; CHECK: ret
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}
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; CHECK-LABEL: mand16
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; CHECK: kandw
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; CHECK: kxorw
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; CHECK: korw
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define i16 @mand16(i16 %x, i16 %y) {
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%ma = bitcast i16 %x to <16 x i1>
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%mb = bitcast i16 %y to <16 x i1>
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@ -59,15 +70,11 @@ define i16 @mand16(i16 %x, i16 %y) {
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%md = xor <16 x i1> %ma, %mb
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%me = or <16 x i1> %mc, %md
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%ret = bitcast <16 x i1> %me to i16
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; CHECK: kandw
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; CHECK: kxorw
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; CHECK: korw
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ret i16 %ret
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}
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; CHECK: shuf_test1
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; CHECK-LABEL: shuf_test1
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; CHECK: kshiftrw $8
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; CHECK:ret
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define i8 @shuf_test1(i16 %v) nounwind {
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%v1 = bitcast i16 %v to <16 x i1>
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%mask = shufflevector <16 x i1> %v1, <16 x i1> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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@ -75,11 +82,11 @@ define i8 @shuf_test1(i16 %v) nounwind {
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ret i8 %mask1
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}
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; CHECK: zext_test1
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; CHECK-LABEL: zext_test1
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; CHECK: kshiftlw
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; CHECK: kshiftrw
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; CHECK: kmovw
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; CHECK:ret
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define i32 @zext_test1(<16 x i32> %a, <16 x i32> %b) {
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%cmp_res = icmp ugt <16 x i32> %a, %b
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%cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
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@ -87,11 +94,11 @@ define i32 @zext_test1(<16 x i32> %a, <16 x i32> %b) {
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ret i32 %res
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}
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; CHECK: zext_test2
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; CHECK-LABEL: zext_test2
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; CHECK: kshiftlw
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; CHECK: kshiftrw
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; CHECK: kmovw
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; CHECK:ret
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define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) {
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%cmp_res = icmp ugt <16 x i32> %a, %b
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%cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
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@ -99,14 +106,29 @@ define i16 @zext_test2(<16 x i32> %a, <16 x i32> %b) {
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ret i16 %res
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}
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; CHECK: zext_test3
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; CHECK-LABEL: zext_test3
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; CHECK: kshiftlw
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; CHECK: kshiftrw
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; CHECK: kmovw
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; CHECK:ret
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|
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define i8 @zext_test3(<16 x i32> %a, <16 x i32> %b) {
|
||||
%cmp_res = icmp ugt <16 x i32> %a, %b
|
||||
%cmp_res.i1 = extractelement <16 x i1> %cmp_res, i32 5
|
||||
%res = zext i1 %cmp_res.i1 to i8
|
||||
ret i8 %res
|
||||
}
|
||||
|
||||
; CHECK-LABEL: conv1
|
||||
; KNL: kmovw %k0, %eax
|
||||
; KNL: movb %al, (%rdi)
|
||||
; SKX: kmovb %k0, (%rdi)
|
||||
define i8 @conv1(<8 x i1>* %R) {
|
||||
entry:
|
||||
store <8 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i1>* %R
|
||||
|
||||
%maskPtr = alloca <8 x i1>
|
||||
store <8 x i1> <i1 0, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>, <8 x i1>* %maskPtr
|
||||
%mask = load <8 x i1>* %maskPtr
|
||||
%mask_convert = bitcast <8 x i1> %mask to i8
|
||||
ret i8 %mask_convert
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user