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ARM assembly parsing for ASR(immediate).

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Start of rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-11-10 16:44:55 +00:00
parent 977665c24a
commit 71810ab7c0
4 changed files with 45 additions and 8 deletions
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20
lib/Target/ARM/ARMInstrFormats.td
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@@ -293,21 +293,27 @@ class InstThumb<AddrMode am, int sz, IndexMode im,
// Pseudo-instructions for alternate assembly syntax (never used by codegen).
// These are aliases that require C++ handling to convert to the target
// instruction, while InstAliases can be handled directly by tblgen.
class AsmPseudoInst<dag iops>
class AsmPseudoInst<string asm, dag iops>
: InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
"", NoItinerary> {
let OutOperandList = (ops);
let OutOperandList = (outs);
let InOperandList = iops;
let Pattern = [];
let isCodeGenOnly = 0; // So we get asm matcher for it.
let AsmString = asm;
let isPseudo = 1;
}
class ARMAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsARM]>;
class tAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsThumb]>;
class t2AsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[IsThumb2]>;
class VFP2AsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[HasVFP2]>;
class NEONAsmPseudo<dag iops> : AsmPseudoInst<iops>, Requires<[HasNEON]>;
class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
Requires<[IsARM]>;
class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
Requires<[IsThumb]>;
class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
Requires<[IsThumb2]>;
class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
Requires<[HasVFP2]>;
class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
Requires<[HasNEON]>;
// Pseudo instructions for the code generator.
class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>