diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index 265a3305a01..d2aa2bb2212 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -738,7 +738,7 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, if (!Reg || IncomingReg == Reg || !TargetRegisterInfo::isPhysicalRegister(Reg) || !TargetRegisterInfo::isPhysicalRegister(IncomingReg)) { - ++i; + ++i; continue; } @@ -748,17 +748,17 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, return true; if (RegInfo->isSubRegister(IncomingReg, Reg) && MO.isKill()) { - if (MO.isImplicit()) { - // Remove this implicit use that marks the sub-register - // "kill". Let the super-register take care of this - // information. - RemoveOperand(i); - --e; - continue; - } else { - // The super-register is going to take care of this kill - // information. - MO.setIsKill(false); + if (MO.isImplicit()) { + // Remove this implicit use that marks the sub-register + // "kill". Let the super-register take care of this + // information. + RemoveOperand(i); + --e; + continue; + } else { + // The super-register is going to take care of this kill + // information. + MO.setIsKill(false); } } } @@ -781,9 +781,9 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, } if (TargetRegisterInfo::isPhysicalRegister(Reg) && - TargetRegisterInfo::isPhysicalRegister(IncomingReg) && - RegInfo->isSuperRegister(IncomingReg, Reg) && - MO.isKill()) + TargetRegisterInfo::isPhysicalRegister(IncomingReg) && + RegInfo->isSuperRegister(IncomingReg, Reg) && + MO.isKill()) // A super-register kill already exists. return true; } diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp index 4a00ea095c9..cb9916ce681 100644 --- a/lib/CodeGen/PrologEpilogInserter.cpp +++ b/lib/CodeGen/PrologEpilogInserter.cpp @@ -520,57 +520,57 @@ void PEI::replaceFrameIndices(MachineFunction &Fn) { if (I->getOpcode() == TargetInstrInfo::DECLARE) { // Ignore it. ++I; - continue; + continue; } if (I->getOpcode() == FrameSetupOpcode || I->getOpcode() == FrameDestroyOpcode) { // Remember how much SP has been adjusted to create the call // frame. - int Size = I->getOperand(0).getImm(); + int Size = I->getOperand(0).getImm(); - if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || - (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) - Size = -Size; + if ((!StackGrowsDown && I->getOpcode() == FrameSetupOpcode) || + (StackGrowsDown && I->getOpcode() == FrameDestroyOpcode)) + Size = -Size; - SPAdj += Size; + SPAdj += Size; - MachineBasicBlock::iterator PrevI = prior(I); - TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); + MachineBasicBlock::iterator PrevI = prior(I); + TRI.eliminateCallFramePseudoInstr(Fn, *BB, I); - // Visit the instructions created by eliminateCallFramePseudoInstr(). - I = next(PrevI); - continue; + // Visit the instructions created by eliminateCallFramePseudoInstr(). + I = next(PrevI); + continue; } bool DoIncr = true; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).isFrameIndex()) { - // Some instructions (e.g. inline asm instructions) can have - // multiple frame indices and/or cause eliminateFrameIndex - // to insert more than one instruction. We need the register - // scavenger to go through all of these instructions so that - // it can update its register information. We keep the - // iterator at the point before insertion so that we can - // revisit them in full. - bool AtBeginning = (I == BB->begin()); - if (!AtBeginning) --I; + if (MI->getOperand(i).isFrameIndex()) { + // Some instructions (e.g. inline asm instructions) can have + // multiple frame indices and/or cause eliminateFrameIndex + // to insert more than one instruction. We need the register + // scavenger to go through all of these instructions so that + // it can update its register information. We keep the + // iterator at the point before insertion so that we can + // revisit them in full. + bool AtBeginning = (I == BB->begin()); + if (!AtBeginning) --I; - // If this instruction has a FrameIndex operand, we need to - // use that target machine register info object to eliminate - // it. - TRI.eliminateFrameIndex(MI, SPAdj, RS); + // If this instruction has a FrameIndex operand, we need to + // use that target machine register info object to eliminate + // it. + TRI.eliminateFrameIndex(MI, SPAdj, RS); - // Reset the iterator if we were at the beginning of the BB. - if (AtBeginning) { - I = BB->begin(); - DoIncr = false; - } + // Reset the iterator if we were at the beginning of the BB. + if (AtBeginning) { + I = BB->begin(); + DoIncr = false; + } - MI = 0; - break; - } + MI = 0; + break; + } if (DoIncr) ++I; diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp index b21355cc9e0..b872a44fec4 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesExpand.cpp @@ -1247,7 +1247,7 @@ void DAGTypeLegalizer::ExpandSetCCOperands(SDOperand &NewLHS, SDOperand &NewRHS, ISD::SETEQ, false, DagCombineInfo); if (!NewLHS.Val) NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, - ISD::SETEQ); + ISD::SETEQ); NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(), NewLHS, Tmp1, Tmp2); NewRHS = SDOperand(); diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp index eef7a83a100..b8118eb0392 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesPromote.cpp @@ -187,9 +187,9 @@ SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) { SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) { assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0))) - && "SetCC type is not legal??"); + && "SetCC type is not legal??"); return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)), - N->getOperand(0), N->getOperand(1), N->getOperand(2)); + N->getOperand(0), N->getOperand(1), N->getOperand(2)); } SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) { diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index bb55024ab21..ff7d42e6c6b 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -366,7 +366,7 @@ PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill, // FIXME (64-bit): Enable NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR)) .addReg(SrcReg, false, false, isKill), - FrameIdx)); + FrameIdx)); return true; } else { // FIXME: We use R0 here, because it isn't available for RA. We need to diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 0970ef66279..d78abaca7c3 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -483,12 +483,12 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, } else if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, TII.get(PPC::LD), Reg) - .addImm(0) - .addReg(PPC::X1); + .addImm(0) + .addReg(PPC::X1); else BuildMI(MBB, II, TII.get(PPC::LD), PPC::X0) - .addImm(0) - .addReg(PPC::X1); + .addImm(0) + .addReg(PPC::X1); } else { BuildMI(MBB, II, TII.get(PPC::LWZ), Reg) .addImm(0) @@ -500,25 +500,25 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, if (LP64) { if (EnableRegisterScavenging) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, TII.get(PPC::STDUX)) - .addReg(Reg, false, false, true) - .addReg(PPC::X1) - .addReg(MI.getOperand(1).getReg()); + .addReg(Reg, false, false, true) + .addReg(PPC::X1) + .addReg(MI.getOperand(1).getReg()); else BuildMI(MBB, II, TII.get(PPC::STDUX)) - .addReg(PPC::X0, false, false, true) - .addReg(PPC::X1) - .addReg(MI.getOperand(1).getReg()); + .addReg(PPC::X0, false, false, true) + .addReg(PPC::X1) + .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) - .addReg(PPC::X1) - .addImm(maxCallFrameSize); + .addReg(PPC::X1) + .addImm(maxCallFrameSize); else // Implicitly kill the register. BuildMI(MBB, II, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) - .addReg(PPC::X1) - .addImm(maxCallFrameSize) - .addReg(MI.getOperand(1).getReg(), false, true, true); + .addReg(PPC::X1) + .addImm(maxCallFrameSize) + .addReg(MI.getOperand(1).getReg(), false, true, true); } else { BuildMI(MBB, II, TII.get(PPC::STWUX)) .addReg(Reg, false, false, true) @@ -527,14 +527,14 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, if (!MI.getOperand(1).isKill()) BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) - .addReg(PPC::R1) - .addImm(maxCallFrameSize); + .addReg(PPC::R1) + .addImm(maxCallFrameSize); else // Implicitly kill the register. BuildMI(MBB, II, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) - .addReg(PPC::R1) - .addImm(maxCallFrameSize) - .addReg(MI.getOperand(1).getReg(), false, true, true); + .addReg(PPC::R1) + .addImm(maxCallFrameSize) + .addReg(MI.getOperand(1).getReg(), false, true, true); } // Discard the DYNALLOC instruction. @@ -945,7 +945,7 @@ PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC; RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment())); + RC->getAlignment())); } } diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp index e5d70cd084e..a570c8f6d2c 100644 --- a/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/utils/TableGen/CodeGenDAGPatterns.cpp @@ -562,9 +562,9 @@ bool TreePatternNode::isIsomorphicTo(const TreePatternNode *N, if (isLeaf()) { if (DefInit *DI = dynamic_cast(getLeafValue())) { if (DefInit *NDI = dynamic_cast(N->getLeafValue())) { - return ((DI->getDef() == NDI->getDef()) - && (DepVars.find(getName()) == DepVars.end() - || getName() == N->getName())); + return ((DI->getDef() == NDI->getDef()) + && (DepVars.find(getName()) == DepVars.end() + || getName() == N->getName())); } } return getLeafValue() == N->getLeafValue();