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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Remove misuse of ReplaceNodeResults for atomics with
valid types. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56808 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1261,9 +1261,6 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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case TargetLowering::Custom:
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case TargetLowering::Custom:
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Result = TLI.LowerOperation(Result, DAG);
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Result = TLI.LowerOperation(Result, DAG);
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break;
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break;
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case TargetLowering::Expand:
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Result = SDValue(TLI.ReplaceNodeResults(Op.getNode(), DAG),0);
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break;
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case TargetLowering::Legal:
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case TargetLowering::Legal:
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break;
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break;
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}
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}
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@ -297,10 +297,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_8, MVT::i8, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_8 , MVT::i8, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Custom);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Expand);
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setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
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// Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
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// Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
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@ -6002,18 +6002,22 @@ SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
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return DAG.getMergeValues(Vals, 2).getNode();
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return DAG.getMergeValues(Vals, 2).getNode();
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}
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}
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SDNode* X86TargetLowering::ExpandATOMIC_LOAD_SUB(SDNode* Op,
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SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
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SelectionDAG &DAG) {
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SDNode *Node = Op.getNode();
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MVT T = Op->getValueType(0);
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MVT T = Node->getValueType(0);
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SDValue negOp = DAG.getNode(ISD::SUB, T,
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SDValue negOp = DAG.getNode(ISD::SUB, T,
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DAG.getConstant(0, T), Op->getOperand(2));
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DAG.getConstant(0, T), Node->getOperand(2));
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return DAG.getAtomic((T==MVT::i8 ? ISD::ATOMIC_LOAD_ADD_8:
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return DAG.getAtomic((Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_8 ?
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T==MVT::i16 ? ISD::ATOMIC_LOAD_ADD_16:
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ISD::ATOMIC_LOAD_ADD_8 :
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T==MVT::i32 ? ISD::ATOMIC_LOAD_ADD_32:
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Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_16 ?
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T==MVT::i64 ? ISD::ATOMIC_LOAD_ADD_64: 0),
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ISD::ATOMIC_LOAD_ADD_16 :
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Op->getOperand(0), Op->getOperand(1), negOp,
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Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_32 ?
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cast<AtomicSDNode>(Op)->getSrcValue(),
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ISD::ATOMIC_LOAD_ADD_32 :
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cast<AtomicSDNode>(Op)->getAlignment()).getNode();
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ISD::ATOMIC_LOAD_ADD_64),
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Node->getOperand(0),
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Node->getOperand(1), negOp,
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cast<AtomicSDNode>(Node)->getSrcValue(),
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cast<AtomicSDNode>(Node)->getAlignment());
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}
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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/// LowerOperation - Provide custom lowering hooks for some operations.
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@ -6025,6 +6029,10 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP_16: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP_32: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
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case ISD::ATOMIC_LOAD_SUB_8: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_LOAD_SUB_16: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
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case ISD::ATOMIC_LOAD_SUB_64: return LowerLOAD_SUB(Op,DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
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@ -6079,10 +6087,6 @@ SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
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case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
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case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
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case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
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case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
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case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
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case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
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case ISD::ATOMIC_LOAD_SUB_8: return ExpandATOMIC_LOAD_SUB(N,DAG);
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case ISD::ATOMIC_LOAD_SUB_16: return ExpandATOMIC_LOAD_SUB(N,DAG);
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case ISD::ATOMIC_LOAD_SUB_32: return ExpandATOMIC_LOAD_SUB(N,DAG);
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case ISD::ATOMIC_LOAD_SUB_64: return ExpandATOMIC_LOAD_SUB(N,DAG);
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}
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}
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}
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}
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@ -569,10 +569,10 @@ namespace llvm {
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SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
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SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG);
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SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandATOMIC_CMP_SWAP(SDNode *N, SelectionDAG &DAG);
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SDNode *ExpandATOMIC_LOAD_SUB(SDNode *N, SelectionDAG &DAG);
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SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
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SDValue EmitTargetCodeForMemset(SelectionDAG &DAG,
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SDValue Chain,
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SDValue Chain,
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