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Extensions of Hexagon V4 instructions.
This adds new instructions for Hexagon V4 architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -375,7 +375,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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};
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};
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ReplaceUses(Froms, Tos, 3);
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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return Result_2;
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}
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}
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, MVT::i32);
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
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SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
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@ -723,7 +723,7 @@ SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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if (AM != ISD::UNINDEXED) {
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if (AM != ISD::UNINDEXED) {
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return SelectIndexedStore(ST, dl);
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return SelectIndexedStore(ST, dl);
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}
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}
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return SelectBaseOffsetStore(ST, dl);
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return SelectBaseOffsetStore(ST, dl);
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}
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}
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@ -1215,7 +1215,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
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// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
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// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
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// Rd and Rd' are assigned to the same register
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// Rd and Rd' are assigned to the same register
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SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_rr_acc, dl, MVT::i32,
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SDNode* Result = CurDAG->getMachineNode(Hexagon::ASR_ADD_rr, dl, MVT::i32,
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N->getOperand(1),
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N->getOperand(1),
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Src1->getOperand(0),
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Src1->getOperand(0),
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Src1->getOperand(1));
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Src1->getOperand(1));
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@ -13,29 +13,48 @@
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// *** Must match HexagonBaseInfo.h ***
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// *** Must match HexagonBaseInfo.h ***
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class Type<bits<5> t> {
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bits<5> Value = t;
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}
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def TypePSEUDO : Type<0>;
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def TypeALU32 : Type<1>;
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def TypeCR : Type<2>;
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def TypeJR : Type<3>;
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def TypeJ : Type<4>;
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def TypeLD : Type<5>;
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def TypeST : Type<6>;
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def TypeSYSTEM : Type<7>;
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def TypeXTYPE : Type<8>;
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def TypeMARKER : Type<31>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Intruction Class Declaration +
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// Intruction Class Declaration +
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr, InstrItinClass itin> : Instruction {
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string cstr, InstrItinClass itin, Type type> : Instruction {
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field bits<32> Inst;
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field bits<32> Inst;
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let Namespace = "Hexagon";
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let Namespace = "Hexagon";
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dag OutOperandList = outs;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Pattern = pattern;
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let Constraints = cstr;
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let Constraints = cstr;
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let Itinerary = itin;
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let Itinerary = itin;
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let Size = 4;
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// *** The code below must match HexagonBaseInfo.h ***
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// *** Must match HexagonBaseInfo.h ***
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// Instruction type according to the ISA.
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Type HexagonType = type;
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let TSFlags{4-0} = HexagonType.Value;
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// Solo instructions, i.e., those that cannot be in a packet with others.
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bits<1> isHexagonSolo = 0;
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let TSFlags{5} = isHexagonSolo;
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// Predicated instructions.
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// Predicated instructions.
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bits<1> isPredicated = 0;
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bits<1> isPredicated = 0;
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let TSFlags{1} = isPredicated;
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let TSFlags{6} = isPredicated;
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// *** The code above must match HexagonBaseInfo.h ***
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// *** The code above must match HexagonBaseInfo.h ***
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}
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}
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@ -47,17 +66,25 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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// LD Instruction Class in V2/V3/V4.
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", LD> {
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: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<13> imm13;
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bits<13> imm13;
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}
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}
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class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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let mayLoad = 1;
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}
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// LD Instruction Class in V2/V3/V4.
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, LD> {
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: InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -68,7 +95,24 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ST> {
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: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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}
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class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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let mayStore = 1;
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}
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// SYSTEM Instruction Class in V4 can take SLOT0 only
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// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
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class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<13> imm13;
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bits<13> imm13;
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@ -79,7 +123,7 @@ class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ST> {
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -89,7 +133,7 @@ class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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// ALU32 Instruction Class in V2/V3/V4.
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// ALU32 Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU32> {
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -102,7 +146,17 @@ class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
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// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
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class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU64> {
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<16> imm16_2;
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}
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class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -115,7 +169,7 @@ class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", M> {
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: InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -126,8 +180,8 @@ class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, M> {
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: InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -138,9 +192,7 @@ class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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//: InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, M)> {
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: InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
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: InstHexagon<outs, ins, asmstr, pattern, "", S> {
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// : InstHexagon<outs, ins, asmstr, pattern, "", S> {
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bits<5> rd;
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bits<5> rd;
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bits<5> rs;
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bits<5> rs;
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bits<5> rt;
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bits<5> rt;
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@ -151,8 +203,8 @@ class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
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: InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
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bits<5> rd;
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bits<5> rd;
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@ -163,14 +215,14 @@ class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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// J Instruction Class in V2/V3/V4.
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// J Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
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class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", J> {
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: InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
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bits<16> imm16;
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bits<16> imm16;
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}
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}
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// JR Instruction Class in V2/V3/V4.
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// JR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
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class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", JR> {
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: InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
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bits<5> rs;
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bits<5> rs;
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bits<5> pu; // Predicate register
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bits<5> pu; // Predicate register
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}
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}
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@ -178,15 +230,22 @@ class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
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// CR Instruction Class in V2/V3/V4.
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// CR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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// Definition of the instruction class NOT CHANGED.
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class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", CR> {
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: InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
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bits<5> rs;
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bits<5> rs;
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bits<10> imm10;
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bits<10> imm10;
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}
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}
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class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>;
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: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Intruction Classes Definitions -
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// Intruction Classes Definitions -
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@ -222,6 +281,11 @@ class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU64Type<outs, ins, asmstr, pattern> {
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: ALU64Type<outs, ins, asmstr, pattern> {
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}
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}
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class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU64Type<outs, ins, asmstr, pattern> {
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let rt{0-4} = 0;
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}
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// J Type Instructions.
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// J Type Instructions.
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class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||||
: JType<outs, ins, asmstr, pattern> {
|
: JType<outs, ins, asmstr, pattern> {
|
||||||
@ -234,17 +298,33 @@ class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|||||||
|
|
||||||
|
|
||||||
// Post increment ST Instruction.
|
// Post increment ST Instruction.
|
||||||
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
|
class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||||
|
string cstr>
|
||||||
: STInstPost<outs, ins, asmstr, pattern, cstr> {
|
: STInstPost<outs, ins, asmstr, pattern, cstr> {
|
||||||
let rt{0-4} = 0;
|
let rt{0-4} = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||||
|
string cstr>
|
||||||
|
: STInstPost<outs, ins, asmstr, pattern, cstr> {
|
||||||
|
let rt{0-4} = 0;
|
||||||
|
let mayStore = 1;
|
||||||
|
}
|
||||||
|
|
||||||
// Post increment LD Instruction.
|
// Post increment LD Instruction.
|
||||||
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern, string cstr>
|
class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||||
|
string cstr>
|
||||||
: LDInstPost<outs, ins, asmstr, pattern, cstr> {
|
: LDInstPost<outs, ins, asmstr, pattern, cstr> {
|
||||||
let rt{0-4} = 0;
|
let rt{0-4} = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||||
|
string cstr>
|
||||||
|
: LDInstPost<outs, ins, asmstr, pattern, cstr> {
|
||||||
|
let rt{0-4} = 0;
|
||||||
|
let mayLoad = 1;
|
||||||
|
}
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// V4 Instruction Format Definitions +
|
// V4 Instruction Format Definitions +
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
@ -11,11 +11,25 @@
|
|||||||
//
|
//
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
//----------------------------------------------------------------------------//
|
||||||
|
// Hexagon Intruction Flags +
|
||||||
|
//
|
||||||
|
// *** Must match BaseInfo.h ***
|
||||||
|
//----------------------------------------------------------------------------//
|
||||||
|
|
||||||
|
def TypeMEMOP : Type<9>;
|
||||||
|
def TypeNV : Type<10>;
|
||||||
|
def TypePREFIX : Type<30>;
|
||||||
|
|
||||||
|
//----------------------------------------------------------------------------//
|
||||||
|
// Intruction Classes Definitions +
|
||||||
|
//----------------------------------------------------------------------------//
|
||||||
|
|
||||||
//
|
//
|
||||||
// NV type instructions.
|
// NV type instructions.
|
||||||
//
|
//
|
||||||
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
|
class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||||
: InstHexagon<outs, ins, asmstr, pattern, "", NV_V4> {
|
: InstHexagon<outs, ins, asmstr, pattern, "", NV_V4, TypeNV> {
|
||||||
bits<5> rd;
|
bits<5> rd;
|
||||||
bits<5> rs;
|
bits<5> rs;
|
||||||
bits<13> imm13;
|
bits<13> imm13;
|
||||||
@ -24,7 +38,7 @@ class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
|
|||||||
// Definition of Post increment new value store.
|
// Definition of Post increment new value store.
|
||||||
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
|
class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
|
||||||
string cstr>
|
string cstr>
|
||||||
: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4> {
|
: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV> {
|
||||||
bits<5> rd;
|
bits<5> rd;
|
||||||
bits<5> rs;
|
bits<5> rs;
|
||||||
bits<5> rt;
|
bits<5> rt;
|
||||||
@ -39,8 +53,15 @@ class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
|
|||||||
}
|
}
|
||||||
|
|
||||||
class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
|
class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||||
: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4> {
|
: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> {
|
||||||
bits<5> rd;
|
bits<5> rd;
|
||||||
bits<5> rs;
|
bits<5> rs;
|
||||||
bits<6> imm6;
|
bits<6> imm6;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
class Immext<dag outs, dag ins, string asmstr, list<dag> pattern>
|
||||||
|
: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX> {
|
||||||
|
let isCodeGenOnly = 1;
|
||||||
|
|
||||||
|
bits<26> imm26;
|
||||||
|
}
|
||||||
|
@ -1200,9 +1200,6 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
|
|||||||
case Hexagon::LDriub:
|
case Hexagon::LDriub:
|
||||||
return !invertPredicate ? Hexagon::LDriub_cPt :
|
return !invertPredicate ? Hexagon::LDriub_cPt :
|
||||||
Hexagon::LDriub_cNotPt;
|
Hexagon::LDriub_cNotPt;
|
||||||
case Hexagon::LDriubit:
|
|
||||||
return !invertPredicate ? Hexagon::LDriub_cPt :
|
|
||||||
Hexagon::LDriub_cNotPt;
|
|
||||||
// Load Indexed.
|
// Load Indexed.
|
||||||
case Hexagon::LDrid_indexed:
|
case Hexagon::LDrid_indexed:
|
||||||
return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
|
return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
|
||||||
@ -1409,7 +1406,6 @@ isValidOffset(const int Opcode, const int Offset) const {
|
|||||||
case Hexagon::LDrih:
|
case Hexagon::LDrih:
|
||||||
case Hexagon::LDriuh:
|
case Hexagon::LDriuh:
|
||||||
case Hexagon::STrih:
|
case Hexagon::STrih:
|
||||||
case Hexagon::LDrih_ae:
|
|
||||||
assert((Offset % 2 == 0) && "Offset has incorrect alignment");
|
assert((Offset % 2 == 0) && "Offset has incorrect alignment");
|
||||||
return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
|
return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
|
||||||
(Offset <= Hexagon_MEMH_OFFSET_MAX);
|
(Offset <= Hexagon_MEMH_OFFSET_MAX);
|
||||||
@ -1417,9 +1413,6 @@ isValidOffset(const int Opcode, const int Offset) const {
|
|||||||
case Hexagon::LDrib:
|
case Hexagon::LDrib:
|
||||||
case Hexagon::STrib:
|
case Hexagon::STrib:
|
||||||
case Hexagon::LDriub:
|
case Hexagon::LDriub:
|
||||||
case Hexagon::LDriubit:
|
|
||||||
case Hexagon::LDrib_ae:
|
|
||||||
case Hexagon::LDriub_ae:
|
|
||||||
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
|
return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
|
||||||
(Offset <= Hexagon_MEMB_OFFSET_MAX);
|
(Offset <= Hexagon_MEMB_OFFSET_MAX);
|
||||||
|
|
||||||
|
File diff suppressed because it is too large
Load Diff
@ -41,10 +41,11 @@ let isCall = 1, neverHasSideEffects = 1,
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
// Jump to address from register
|
||||||
// if(p?.new) jumpr:t r?
|
// if(p?.new) jumpr:t r?
|
||||||
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
||||||
Defs = [PC], Uses = [R31] in {
|
Defs = [PC], Uses = [R31] in {
|
||||||
def JMPR_cPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
def JMPR_cdnPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
||||||
"if ($src1.new) jumpr:t $src2",
|
"if ($src1.new) jumpr:t $src2",
|
||||||
[]>, Requires<[HasV3T]>;
|
[]>, Requires<[HasV3T]>;
|
||||||
}
|
}
|
||||||
@ -52,7 +53,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
|||||||
// if (!p?.new) jumpr:t r?
|
// if (!p?.new) jumpr:t r?
|
||||||
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
||||||
Defs = [PC], Uses = [R31] in {
|
Defs = [PC], Uses = [R31] in {
|
||||||
def JMPR_cNotPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
def JMPR_cdnNotPt_V3: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
||||||
"if (!$src1.new) jumpr:t $src2",
|
"if (!$src1.new) jumpr:t $src2",
|
||||||
[]>, Requires<[HasV3T]>;
|
[]>, Requires<[HasV3T]>;
|
||||||
}
|
}
|
||||||
@ -61,7 +62,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
|||||||
// if(p?.new) jumpr:nt r?
|
// if(p?.new) jumpr:nt r?
|
||||||
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
||||||
Defs = [PC], Uses = [R31] in {
|
Defs = [PC], Uses = [R31] in {
|
||||||
def JMPR_cPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
def JMPR_cdnPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
||||||
"if ($src1.new) jumpr:nt $src2",
|
"if ($src1.new) jumpr:nt $src2",
|
||||||
[]>, Requires<[HasV3T]>;
|
[]>, Requires<[HasV3T]>;
|
||||||
}
|
}
|
||||||
@ -69,7 +70,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
|||||||
// if (!p?.new) jumpr:nt r?
|
// if (!p?.new) jumpr:nt r?
|
||||||
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
let isReturn = 1, isTerminator = 1, isBarrier = 1,
|
||||||
Defs = [PC], Uses = [R31] in {
|
Defs = [PC], Uses = [R31] in {
|
||||||
def JMPR_cNotPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
def JMPR_cdnNotPnt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
|
||||||
"if (!$src1.new) jumpr:nt $src2",
|
"if (!$src1.new) jumpr:nt $src2",
|
||||||
[]>, Requires<[HasV3T]>;
|
[]>, Requires<[HasV3T]>;
|
||||||
}
|
}
|
||||||
@ -86,20 +87,22 @@ let AddedComplexity = 200 in
|
|||||||
def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
|
def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
|
||||||
DoubleRegs:$src2),
|
DoubleRegs:$src2),
|
||||||
"$dst = max($src2, $src1)",
|
"$dst = max($src2, $src1)",
|
||||||
[(set DoubleRegs:$dst, (select (i1 (setlt DoubleRegs:$src2,
|
[(set (i64 DoubleRegs:$dst),
|
||||||
DoubleRegs:$src1)),
|
(i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
|
||||||
DoubleRegs:$src1,
|
(i64 DoubleRegs:$src1))),
|
||||||
DoubleRegs:$src2))]>,
|
(i64 DoubleRegs:$src1),
|
||||||
|
(i64 DoubleRegs:$src2))))]>,
|
||||||
Requires<[HasV3T]>;
|
Requires<[HasV3T]>;
|
||||||
|
|
||||||
let AddedComplexity = 200 in
|
let AddedComplexity = 200 in
|
||||||
def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
|
def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
|
||||||
DoubleRegs:$src2),
|
DoubleRegs:$src2),
|
||||||
"$dst = min($src2, $src1)",
|
"$dst = min($src2, $src1)",
|
||||||
[(set DoubleRegs:$dst, (select (i1 (setgt DoubleRegs:$src2,
|
[(set (i64 DoubleRegs:$dst),
|
||||||
DoubleRegs:$src1)),
|
(i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
|
||||||
DoubleRegs:$src1,
|
(i64 DoubleRegs:$src1))),
|
||||||
DoubleRegs:$src2))]>,
|
(i64 DoubleRegs:$src1),
|
||||||
|
(i64 DoubleRegs:$src2))))]>,
|
||||||
Requires<[HasV3T]>;
|
Requires<[HasV3T]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
@ -109,25 +112,25 @@ Requires<[HasV3T]>;
|
|||||||
|
|
||||||
|
|
||||||
|
|
||||||
//def : Pat <(brcond (i1 (seteq IntRegs:$src1, 0)), bb:$offset),
|
//def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
|
||||||
// (JMP_RegEzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
|
// (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
|
||||||
|
|
||||||
//def : Pat <(brcond (i1 (setne IntRegs:$src1, 0)), bb:$offset),
|
//def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
|
||||||
// (JMP_RegNzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
|
// (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
|
||||||
|
|
||||||
//def : Pat <(brcond (i1 (setle IntRegs:$src1, 0)), bb:$offset),
|
//def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
|
||||||
// (JMP_RegLezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
|
// (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
|
||||||
|
|
||||||
//def : Pat <(brcond (i1 (setge IntRegs:$src1, 0)), bb:$offset),
|
//def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
|
||||||
// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
|
// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
|
||||||
|
|
||||||
//def : Pat <(brcond (i1 (setgt IntRegs:$src1, -1)), bb:$offset),
|
//def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
|
||||||
// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
|
// (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
|
||||||
|
|
||||||
|
|
||||||
// Map call instruction
|
// Map call instruction
|
||||||
def : Pat<(call IntRegs:$dst),
|
def : Pat<(call (i32 IntRegs:$dst)),
|
||||||
(CALLRv3 IntRegs:$dst)>, Requires<[HasV3T]>;
|
(CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
|
||||||
def : Pat<(call tglobaladdr:$dst),
|
def : Pat<(call tglobaladdr:$dst),
|
||||||
(CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
|
(CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
|
||||||
def : Pat<(call texternalsym:$dst),
|
def : Pat<(call texternalsym:$dst),
|
||||||
|
File diff suppressed because it is too large
Load Diff
@ -13,7 +13,6 @@ def LSUNIT : FuncUnit;
|
|||||||
def MUNIT : FuncUnit;
|
def MUNIT : FuncUnit;
|
||||||
def SUNIT : FuncUnit;
|
def SUNIT : FuncUnit;
|
||||||
|
|
||||||
|
|
||||||
// Itinerary classes
|
// Itinerary classes
|
||||||
def ALU32 : InstrItinClass;
|
def ALU32 : InstrItinClass;
|
||||||
def ALU64 : InstrItinClass;
|
def ALU64 : InstrItinClass;
|
||||||
@ -24,23 +23,25 @@ def LD : InstrItinClass;
|
|||||||
def M : InstrItinClass;
|
def M : InstrItinClass;
|
||||||
def ST : InstrItinClass;
|
def ST : InstrItinClass;
|
||||||
def S : InstrItinClass;
|
def S : InstrItinClass;
|
||||||
|
def SYS : InstrItinClass;
|
||||||
|
def MARKER : InstrItinClass;
|
||||||
def PSEUDO : InstrItinClass;
|
def PSEUDO : InstrItinClass;
|
||||||
|
|
||||||
|
|
||||||
def HexagonItineraries :
|
def HexagonItineraries :
|
||||||
ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
|
ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
|
||||||
InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
|
InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
|
||||||
InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
|
InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
|
||||||
InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
|
InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
|
||||||
InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
|
InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
|
||||||
InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
|
InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
|
||||||
InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
|
InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
|
||||||
InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
|
InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
|
||||||
InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
|
InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
|
||||||
InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
|
InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
|
||||||
InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
|
InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
|
||||||
]>;
|
InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
|
||||||
|
InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
|
||||||
|
]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// V4 Machine Info +
|
// V4 Machine Info +
|
||||||
|
@ -23,7 +23,6 @@
|
|||||||
// | SLOT3 | XTYPE ALU32 J CR |
|
// | SLOT3 | XTYPE ALU32 J CR |
|
||||||
// |===========|==================================================|
|
// |===========|==================================================|
|
||||||
|
|
||||||
|
|
||||||
// Functional Units.
|
// Functional Units.
|
||||||
def SLOT0 : FuncUnit;
|
def SLOT0 : FuncUnit;
|
||||||
def SLOT1 : FuncUnit;
|
def SLOT1 : FuncUnit;
|
||||||
@ -34,22 +33,26 @@ def SLOT3 : FuncUnit;
|
|||||||
def NV_V4 : InstrItinClass;
|
def NV_V4 : InstrItinClass;
|
||||||
def MEM_V4 : InstrItinClass;
|
def MEM_V4 : InstrItinClass;
|
||||||
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
|
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
|
||||||
|
def PREFIX : InstrItinClass;
|
||||||
|
|
||||||
def HexagonItinerariesV4 : ProcessorItineraries<
|
def HexagonItinerariesV4 :
|
||||||
[SLOT0, SLOT1, SLOT2, SLOT3], [], [
|
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3], [], [
|
||||||
InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||||
InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||||
InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,
|
||||||
InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,
|
InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||||
InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,
|
InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,
|
||||||
InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||||
InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,
|
InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||||
InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,
|
InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||||
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||||
InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>,
|
||||||
InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,
|
||||||
InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>
|
InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,
|
||||||
]>;
|
InstrItinData<MARKER , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||||
|
InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||||
|
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>
|
||||||
|
]>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// Hexagon V4 Resource Definitions -
|
// Hexagon V4 Resource Definitions -
|
||||||
|
Loading…
Reference in New Issue
Block a user