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fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26416 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -23,9 +23,6 @@
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// FIXME: mul (x, const) -> shifts + adds
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// FIXME: undef values
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// FIXME: make truncate see through SIGN_EXTEND and AND
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// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
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// FIXME: verify that getNode can't return extends with an operand whose type
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// is >= to that of the extend.
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// FIXME: divide by zero is currently left unfolded. do we want to turn this
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// into an undef?
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// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
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@ -1367,6 +1364,17 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
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DAG.getValueType(EVT));
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}
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// fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
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if (N1C && N0.getOpcode() == ISD::SRA) {
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if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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unsigned Sum = N1C->getValue() + C1->getValue();
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if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
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return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
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DAG.getConstant(Sum, N1C->getValueType(0)));
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}
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}
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// If the sign bit is known to be zero, switch this to a SRL.
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if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
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return DAG.getNode(ISD::SRL, VT, N0, N1);
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