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Remove the -disable-16bit command-line option, which is now obsolete.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-04-30 18:30:26 +00:00
parent 132dace4aa
commit 71edb241a1
3 changed files with 7 additions and 53 deletions
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22
lib/Target/X86/X86ISelLowering.cpp
View File

@ -57,14 +57,6 @@ STATISTIC(NumTailCalls, "Number of tail calls");
static cl::opt<bool>
DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
// Disable16Bit - 16-bit operations typically have a larger encoding than
// corresponding 32-bit instructions, and 16-bit code is slow on some
// processors. This is an experimental flag to disable 16-bit operations
// (which forces them to be Legalized to 32-bit operations).
static cl::opt<bool>
Disable16Bit("disable-16bit", cl::Hidden,
cl::desc("Disable use of 16-bit instructions"));
// Forward declarations.
static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
SDValue V2);
@ -120,7 +112,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// Set up the register classes.
addRegisterClass(MVT::i8, X86::GR8RegisterClass);
if (!Disable16Bit)
addRegisterClass(MVT::i16, X86::GR16RegisterClass);
addRegisterClass(MVT::i32, X86::GR32RegisterClass);
if (Subtarget->is64Bit())
@ -130,10 +121,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// We don't accept any truncstore of integer registers.
setTruncStoreAction(MVT::i64, MVT::i32, Expand);
if (!Disable16Bit)
setTruncStoreAction(MVT::i64, MVT::i16, Expand);
setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
if (!Disable16Bit)
setTruncStoreAction(MVT::i32, MVT::i16, Expand);
setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
setTruncStoreAction(MVT::i16, MVT::i8, Expand);
@ -285,13 +274,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
if (Disable16Bit) {
setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
} else {
setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
}
setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
@ -308,18 +292,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
// X86 wants to expand cmov itself.
setOperationAction(ISD::SELECT , MVT::i8 , Custom);
if (Disable16Bit)
setOperationAction(ISD::SELECT , MVT::i16 , Expand);
else
setOperationAction(ISD::SELECT , MVT::i16 , Custom);
setOperationAction(ISD::SELECT , MVT::i32 , Custom);
setOperationAction(ISD::SELECT , MVT::f32 , Custom);
setOperationAction(ISD::SELECT , MVT::f64 , Custom);
setOperationAction(ISD::SELECT , MVT::f80 , Custom);
setOperationAction(ISD::SETCC , MVT::i8 , Custom);
if (Disable16Bit)
setOperationAction(ISD::SETCC , MVT::i16 , Expand);
else
setOperationAction(ISD::SETCC , MVT::i16 , Custom);
setOperationAction(ISD::SETCC , MVT::i32 , Custom);
setOperationAction(ISD::SETCC , MVT::f32 , Custom);

12
lib/Target/X86/X86Instr64bit.td
View File

@ -2337,15 +2337,3 @@ let isTwoAddress = 1 in {
}
defm PINSRQ : SS41I_insert64<0x22, "pinsrq">;
// -disable-16bit support.
def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
(MOV16mi addr:$dst, imm:$src)>;
def : Pat<(truncstorei16 GR64:$src, addr:$dst),
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR64:$src, x86_subreg_16bit))>;
def : Pat<(i64 (sextloadi16 addr:$dst)),
(MOVSX64rm16 addr:$dst)>;
def : Pat<(i64 (zextloadi16 addr:$dst)),
(MOVZX64rm16 addr:$dst)>;
def : Pat<(i64 (extloadi16 addr:$dst)),
(MOVZX64rm16 addr:$dst)>;

12
lib/Target/X86/X86InstrInfo.td
View File

@ -4792,18 +4792,6 @@ def : Pat<(and GR16:$src1, i16immSExt8:$src2),
def : Pat<(and GR32:$src1, i32immSExt8:$src2),
(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
// -disable-16bit support.
def : Pat<(truncstorei16 (i16 imm:$src), addr:$dst),
(MOV16mi addr:$dst, imm:$src)>;
def : Pat<(truncstorei16 GR32:$src, addr:$dst),
(MOV16mr addr:$dst, (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
def : Pat<(i32 (sextloadi16 addr:$dst)),
(MOVSX32rm16 addr:$dst)>;
def : Pat<(i32 (zextloadi16 addr:$dst)),
(MOVZX32rm16 addr:$dst)>;
def : Pat<(i32 (extloadi16 addr:$dst)),
(MOVZX32rm16 addr:$dst)>;
//===----------------------------------------------------------------------===//
// Floating Point Stack Support
//===----------------------------------------------------------------------===//