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https://github.com/c64scene-ar/llvm-6502.git
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Use uint16_t to store opcodes in static tables in X86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152391 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -570,8 +570,8 @@ void FPS::finishBlockStack() {
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namespace {
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struct TableEntry {
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unsigned from;
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unsigned to;
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uint16_t from;
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uint16_t to;
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bool operator<(const TableEntry &TE) const { return from < TE.from; }
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friend bool operator<(const TableEntry &TE, unsigned V) {
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return TE.from < V;
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@ -1654,7 +1654,7 @@ enum AtomicSz {
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AtomicSzEnd
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};
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static const unsigned int AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
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{
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X86::LOCK_OR8mi,
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X86::LOCK_OR8mr,
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@ -82,6 +82,12 @@ enum {
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TB_FOLDED_STORE = 1 << 19
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};
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struct X86OpTblEntry {
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uint16_t RegOp;
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uint16_t MemOp;
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uint32_t Flags;
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};
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X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
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? X86::ADJCALLSTACKDOWN64
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@ -91,7 +97,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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: X86::ADJCALLSTACKUP32)),
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TM(tm), RI(tm, *this) {
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static const unsigned OpTbl2Addr[][3] = {
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static const X86OpTblEntry OpTbl2Addr[] = {
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{ X86::ADC32ri, X86::ADC32mi, 0 },
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{ X86::ADC32ri8, X86::ADC32mi8, 0 },
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{ X86::ADC32rr, X86::ADC32mr, 0 },
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@ -259,16 +265,16 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
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unsigned RegOp = OpTbl2Addr[i][0];
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unsigned MemOp = OpTbl2Addr[i][1];
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unsigned Flags = OpTbl2Addr[i][2];
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unsigned RegOp = OpTbl2Addr[i].RegOp;
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unsigned MemOp = OpTbl2Addr[i].MemOp;
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unsigned Flags = OpTbl2Addr[i].Flags;
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AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
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RegOp, MemOp,
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// Index 0, folded load and store, no alignment requirement.
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Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
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}
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static const unsigned OpTbl0[][3] = {
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static const X86OpTblEntry OpTbl0[] = {
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{ X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
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{ X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
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{ X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
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@ -370,14 +376,14 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
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unsigned RegOp = OpTbl0[i][0];
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unsigned MemOp = OpTbl0[i][1];
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unsigned Flags = OpTbl0[i][2];
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unsigned RegOp = OpTbl0[i].RegOp;
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unsigned MemOp = OpTbl0[i].MemOp;
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unsigned Flags = OpTbl0[i].Flags;
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AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
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RegOp, MemOp, TB_INDEX_0 | Flags);
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}
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static const unsigned OpTbl1[][3] = {
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static const X86OpTblEntry OpTbl1[] = {
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{ X86::CMP16rr, X86::CMP16rm, 0 },
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{ X86::CMP32rr, X86::CMP32rm, 0 },
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{ X86::CMP64rr, X86::CMP64rm, 0 },
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@ -555,16 +561,16 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
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unsigned RegOp = OpTbl1[i][0];
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unsigned MemOp = OpTbl1[i][1];
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unsigned Flags = OpTbl1[i][2];
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unsigned RegOp = OpTbl1[i].RegOp;
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unsigned MemOp = OpTbl1[i].MemOp;
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unsigned Flags = OpTbl1[i].Flags;
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AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
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RegOp, MemOp,
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// Index 1, folded load
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Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
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}
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static const unsigned OpTbl2[][3] = {
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static const X86OpTblEntry OpTbl2[] = {
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{ X86::ADC32rr, X86::ADC32rm, 0 },
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{ X86::ADC64rr, X86::ADC64rm, 0 },
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{ X86::ADD16rr, X86::ADD16rm, 0 },
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@ -1108,9 +1114,9 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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};
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for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
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unsigned RegOp = OpTbl2[i][0];
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unsigned MemOp = OpTbl2[i][1];
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unsigned Flags = OpTbl2[i][2];
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unsigned RegOp = OpTbl2[i].RegOp;
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unsigned MemOp = OpTbl2[i].MemOp;
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unsigned Flags = OpTbl2[i].Flags;
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AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
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RegOp, MemOp,
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// Index 2, folded load
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@ -3627,7 +3633,7 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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// These are the replaceable SSE instructions. Some of these have Int variants
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// that we don't include here. We don't want to replace instructions selected
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// by intrinsics.
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static const unsigned ReplaceableInstrs[][3] = {
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static const uint16_t ReplaceableInstrs[][3] = {
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//PackedSingle PackedDouble PackedInt
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{ X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
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{ X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
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@ -3667,7 +3673,7 @@ static const unsigned ReplaceableInstrs[][3] = {
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{ X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
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};
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static const unsigned ReplaceableInstrsAVX2[][3] = {
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static const uint16_t ReplaceableInstrsAVX2[][3] = {
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//PackedSingle PackedDouble PackedInt
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{ X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
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{ X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
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@ -3688,14 +3694,14 @@ static const unsigned ReplaceableInstrsAVX2[][3] = {
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// FIXME: Some shuffle and unpack instructions have equivalents in different
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// domains, but they require a bit more work than just switching opcodes.
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static const unsigned *lookup(unsigned opcode, unsigned domain) {
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static const uint16_t *lookup(unsigned opcode, unsigned domain) {
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for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
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if (ReplaceableInstrs[i][domain-1] == opcode)
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return ReplaceableInstrs[i];
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return 0;
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}
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static const unsigned *lookupAVX2(unsigned opcode, unsigned domain) {
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static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
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for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
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if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
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return ReplaceableInstrsAVX2[i];
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@ -3718,7 +3724,7 @@ void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
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assert(Domain>0 && Domain<4 && "Invalid execution domain");
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uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
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assert(dom && "Not an SSE instruction");
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const unsigned *table = lookup(MI->getOpcode(), dom);
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const uint16_t *table = lookup(MI->getOpcode(), dom);
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if (!table) { // try the other table
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assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
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"256-bit vector operations only available in AVX2");
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