mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add support for 12 bit displacements
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75988 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
078e007c07
commit
720e3b00b8
@ -77,6 +77,10 @@ namespace {
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SystemZTargetLowering &Lowering;
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const SystemZSubtarget &Subtarget;
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void getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index);
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public:
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SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
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: SelectionDAGISel(TM, OptLevel),
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@ -109,13 +113,16 @@ namespace {
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SDValue &Base, SDValue &Disp);
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bool SelectAddrRI(const SDValue& Op, SDValue& Addr,
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SDValue &Base, SDValue &Disp);
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bool SelectAddrRRI(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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bool SelectAddrRRI12(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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bool SelectAddrRRI20(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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bool SelectLAAddr(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index);
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SDNode *Select(SDValue Op);
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bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, unsigned Depth = 0);
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bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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bool is12Bit, unsigned Depth = 0);
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bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);
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#ifndef NDEBUG
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@ -155,24 +162,26 @@ static bool isImmSExt20(SDValue Op, int64_t &Imm) {
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return isImmSExt20(Op.getNode(), Imm);
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}
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/// isImmSExt12 - This method tests to see if the node is either a 32-bit
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/// isImmZExt12 - This method tests to see if the node is either a 32-bit
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/// or 64-bit immediate, and if the value can be accurately represented as a
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/// zero extension from a 12-bit value. If so, this returns true and the
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/// immediate.
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static bool isImmZExt12(SDNode *N, uint64_t &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
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if (Val <= 0xFFF) {
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static bool isImmZExt12(int64_t Val, int64_t &Imm) {
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if (Val >= 0 && Val <= 0xFFF) {
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Imm = Val;
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return true;
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}
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return false;
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}
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static bool isImmZExt12(SDValue Op, uint64_t &Imm) {
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static bool isImmZExt12(SDNode *N, int64_t &Imm) {
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if (N->getOpcode() != ISD::Constant)
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return false;
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return isImmZExt12(cast<ConstantSDNode>(N)->getSExtValue(), Imm);
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}
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static bool isImmZExt12(SDValue Op, int64_t &Imm) {
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return isImmZExt12(Op.getNode(), Imm);
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}
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@ -185,7 +194,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr,
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MVT VT = Addr.getValueType();
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if (Addr.getOpcode() == ISD::ADD) {
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uint64_t Imm = 0;
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int64_t Imm = 0;
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if (isImmZExt12(Addr.getOperand(1), Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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if (FrameIndexSDNode *FI =
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@ -197,7 +206,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr,
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return true; // [r+i]
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}
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} else if (Addr.getOpcode() == ISD::OR) {
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uint64_t Imm = 0;
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int64_t Imm = 0;
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if (isImmZExt12(Addr.getOperand(1), Imm)) {
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// If this is an or of disjoint bitfields, we can codegen this as an add
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// (for better address arithmetic) if the LHS and RHS of the OR are
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@ -221,7 +230,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI32(const SDValue& Op, SDValue& Addr,
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// If this address fits entirely in a 12-bit zext immediate field, codegen
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// this as "d(r0)"
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uint64_t Imm;
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int64_t Imm;
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if (isImmZExt12(CN, Imm)) {
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Disp = CurDAG->getTargetConstant(Imm, MVT::i64);
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Base = CurDAG->getRegister(0, VT);
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@ -302,7 +311,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode.
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bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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unsigned Depth) {
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bool is12Bit, unsigned Depth) {
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DebugLoc dl = N.getDebugLoc();
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DOUT << "MatchAddress: "; DEBUG(AM.dump());
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// Limit recursion.
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@ -317,7 +326,10 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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case ISD::Constant: {
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int64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
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int64_t Imm;
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if (isImmSExt20(AM.Disp + Val, Imm)) {
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bool Match = (is12Bit ?
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isImmZExt12(AM.Disp + Val, Imm) :
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isImmSExt20(AM.Disp + Val, Imm));
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if (Match) {
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AM.Disp = Imm;
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return false;
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}
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@ -325,8 +337,8 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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}
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case ISD::FrameIndex:
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if (AM.BaseType == SystemZRRIAddressMode::RegBase
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&& AM.Base.Reg.getNode() == 0) {
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if (AM.BaseType == SystemZRRIAddressMode::RegBase &&
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AM.Base.Reg.getNode() == 0) {
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AM.BaseType = SystemZRRIAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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@ -343,7 +355,7 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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// Test if the LHS of the sub can be folded.
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SystemZRRIAddressMode Backup = AM;
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if (MatchAddress(N.getNode()->getOperand(0), AM, Depth+1)) {
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if (MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1)) {
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AM = Backup;
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break;
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}
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@ -383,12 +395,12 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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case ISD::ADD: {
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SystemZRRIAddressMode Backup = AM;
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if (!MatchAddress(N.getNode()->getOperand(0), AM, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(1), AM, Depth+1))
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if (!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1))
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return false;
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AM = Backup;
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if (!MatchAddress(N.getNode()->getOperand(1), AM, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(0), AM, Depth+1))
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if (!MatchAddress(N.getNode()->getOperand(1), AM, is12Bit, Depth+1) &&
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!MatchAddress(N.getNode()->getOperand(0), AM, is12Bit, Depth+1))
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return false;
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AM = Backup;
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@ -410,10 +422,13 @@ bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
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SystemZRRIAddressMode Backup = AM;
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int64_t Offset = CN->getSExtValue();
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int64_t Imm;
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// Start with the LHS as an addr mode.
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if (!MatchAddress(N.getOperand(0), AM, Depth+1) &&
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// The resultant disp must fit in 20-bits.
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isImmSExt20(AM.Disp + Offset, Imm) &&
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bool MatchOffset = (is12Bit ?
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isImmZExt12(AM.Disp + Offset, Imm) :
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isImmSExt20(AM.Disp + Offset, Imm));
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// The resultant disp must fit in 12 or 20-bits.
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if (MatchOffset &&
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// LHS should be an addr mode.
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!MatchAddress(N.getOperand(0), AM, is12Bit, Depth+1) &&
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// Check to see if the LHS & C is zero.
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CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
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AM.Disp = Imm;
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@ -449,9 +464,69 @@ bool SystemZDAGToDAGISel::MatchAddressBase(SDValue N,
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return false;
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}
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void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM,
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SDValue &Base, SDValue &Disp,
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SDValue &Index) {
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if (AM.BaseType == SystemZRRIAddressMode::RegBase)
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Base = AM.Base.Reg;
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else
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Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
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Index = AM.IndexReg;
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
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}
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/// Returns true if the address can be represented by a base register plus
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/// index register plus an unsigned 12-bit displacement [base + idx + imm].
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bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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SystemZRRIAddressMode AM20, AM12;
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bool Done = false;
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if (!Addr.hasOneUse()) {
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unsigned Opcode = Addr.getOpcode();
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if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex) {
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// If we are able to fold N into addressing mode, then we'll allow it even
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// if N has multiple uses. In general, addressing computation is used as
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// addresses by all of its uses. But watch out for CopyToReg uses, that
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// means the address computation is liveout. It will be computed by a LA
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// so we want to avoid computing the address twice.
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for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
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UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
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if (UI->getOpcode() == ISD::CopyToReg) {
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MatchAddressBase(Addr, AM12);
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Done = true;
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break;
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}
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}
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}
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}
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if (!Done && MatchAddress(Addr, AM12, /* is12Bit */ true))
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return false;
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// Check, whether we can match stuff using 20-bit displacements
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if (!Done && !MatchAddress(Addr, AM20, /* is12Bit */ false))
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if (AM12.Disp == 0 && AM20.Disp != 0)
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return false;
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DOUT << "MatchAddress (final): "; DEBUG(AM12.dump());
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MVT VT = Addr.getValueType();
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if (AM12.BaseType == SystemZRRIAddressMode::RegBase) {
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if (!AM12.Base.Reg.getNode())
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AM12.Base.Reg = CurDAG->getRegister(0, VT);
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}
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if (!AM12.IndexReg.getNode())
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AM12.IndexReg = CurDAG->getRegister(0, VT);
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getAddressOperands(AM12, Base, Disp, Index);
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return true;
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}
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/// Returns true if the address can be represented by a base register plus
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/// index register plus a signed 20-bit displacement [base + idx + imm].
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bool SystemZDAGToDAGISel::SelectAddrRRI(SDValue Op, SDValue Addr,
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bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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SystemZRRIAddressMode AM;
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bool Done = false;
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@ -474,7 +549,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI(SDValue Op, SDValue Addr,
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}
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}
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}
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if (!Done && MatchAddress(Addr, AM))
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if (!Done && MatchAddress(Addr, AM, /* is12Bit */ false))
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return false;
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DOUT << "MatchAddress (final): "; DEBUG(AM.dump());
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@ -488,12 +563,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI(SDValue Op, SDValue Addr,
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if (!AM.IndexReg.getNode())
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AM.IndexReg = CurDAG->getRegister(0, VT);
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if (AM.BaseType == SystemZRRIAddressMode::RegBase)
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Base = AM.Base.Reg;
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else
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Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy());
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Index = AM.IndexReg;
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
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getAddressOperands(AM, Base, Disp, Index);
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return true;
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}
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@ -504,7 +574,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
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SDValue &Base, SDValue &Disp, SDValue &Index) {
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SystemZRRIAddressMode AM;
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if (MatchAddress(Addr, AM))
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if (MatchAddress(Addr, AM, false))
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return false;
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MVT VT = Addr.getValueType();
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@ -526,13 +596,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr,
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Complexity += 1;
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if (Complexity > 2) {
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if (AM.BaseType == SystemZRRIAddressMode::RegBase)
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Base = AM.Base.Reg;
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else
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Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex,
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TLI.getPointerTy());
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Index = AM.IndexReg;
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Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64);
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getAddressOperands(AM, Base, Disp, Index);
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return true;
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}
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@ -222,21 +222,27 @@ def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
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}
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let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
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def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"ly\t{$dst, $src}",
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[(set GR32:$dst, (load rriaddr:$src))]>;
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def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lg\t{$dst, $src}",
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[(set GR64:$dst, (load rriaddr:$src))]>;
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def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
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"l\t{$dst, $src}",
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[(set GR32:$dst, (load rriaddr12:$src))]>;
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def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"ly\t{$dst, $src}",
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[(set GR32:$dst, (load rriaddr:$src))]>;
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def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lg\t{$dst, $src}",
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[(set GR64:$dst, (load rriaddr:$src))]>;
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}
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def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
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"sty\t{$src, $dst}",
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[(store GR32:$src, rriaddr:$dst)]>;
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def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
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"stg\t{$src, $dst}",
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[(store GR64:$src, rriaddr:$dst)]>;
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def MOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
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"st\t{$src, $dst}",
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[(store GR32:$src, rriaddr12:$dst)]>;
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def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
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"sty\t{$src, $dst}",
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[(store GR32:$src, rriaddr:$dst)]>;
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def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
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"stg\t{$src, $dst}",
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[(store GR64:$src, rriaddr:$dst)]>;
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// FIXME: displacements here are really 12 bit, not 20!
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def MOV8mi : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
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@ -271,21 +277,24 @@ def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
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[(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
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// extloads
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def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"lb\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
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def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"lb\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
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def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
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"lh\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
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def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"lhy\t{$dst, $src}",
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[(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
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def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgb\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
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def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgh\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
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def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgf\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
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def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgb\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
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def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgh\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
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def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
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"lgf\t{$dst, $src}",
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[(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
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def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
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"llc\t{$dst, $src}",
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@ -304,26 +313,45 @@ def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
|
||||
[(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
|
||||
|
||||
// truncstores
|
||||
// FIXME: Implement 12-bit displacement stuff someday
|
||||
def MOV32m8r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
|
||||
"stcy\t{$src, $dst}",
|
||||
[(truncstorei8 GR32:$src, rriaddr:$dst)]>;
|
||||
def MOV32m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
|
||||
"stc\t{$src, $dst}",
|
||||
[(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
|
||||
|
||||
def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
|
||||
"sthy\t{$src, $dst}",
|
||||
[(truncstorei16 GR32:$src, rriaddr:$dst)]>;
|
||||
def MOV32m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
|
||||
"stcy\t{$src, $dst}",
|
||||
[(truncstorei8 GR32:$src, rriaddr:$dst)]>;
|
||||
|
||||
def MOV64m8r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"stcy\t{$src, $dst}",
|
||||
[(truncstorei8 GR64:$src, rriaddr:$dst)]>;
|
||||
def MOV32m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
|
||||
"sth\t{$src, $dst}",
|
||||
[(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
|
||||
|
||||
def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"sthy\t{$src, $dst}",
|
||||
[(truncstorei16 GR64:$src, rriaddr:$dst)]>;
|
||||
def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
|
||||
"sthy\t{$src, $dst}",
|
||||
[(truncstorei16 GR32:$src, rriaddr:$dst)]>;
|
||||
|
||||
def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"sty\t{$src, $dst}",
|
||||
[(truncstorei32 GR64:$src, rriaddr:$dst)]>;
|
||||
def MOV64m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
|
||||
"stc\t{$src, $dst}",
|
||||
[(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
|
||||
|
||||
def MOV64m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"stcy\t{$src, $dst}",
|
||||
[(truncstorei8 GR64:$src, rriaddr:$dst)]>;
|
||||
|
||||
def MOV64m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
|
||||
"sth\t{$src, $dst}",
|
||||
[(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
|
||||
|
||||
def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"sthy\t{$src, $dst}",
|
||||
[(truncstorei16 GR64:$src, rriaddr:$dst)]>;
|
||||
|
||||
def MOV64m32r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
|
||||
"st\t{$src, $dst}",
|
||||
[(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
|
||||
|
||||
def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
|
||||
"sty\t{$src, $dst}",
|
||||
[(truncstorei32 GR64:$src, rriaddr:$dst)]>;
|
||||
|
||||
// multiple regs moves
|
||||
// FIXME: should we use multiple arg nodes?
|
||||
@ -537,12 +565,15 @@ def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
|
||||
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
|
||||
Requires<[IsZ10]>;
|
||||
|
||||
def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
||||
"msy\t{$dst, $src2}",
|
||||
[(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
|
||||
def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
||||
"msg\t{$dst, $src2}",
|
||||
[(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
|
||||
def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
|
||||
"ms\t{$dst, $src2}",
|
||||
[(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
|
||||
def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
|
||||
"msy\t{$dst, $src2}",
|
||||
[(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
|
||||
def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
|
||||
"msg\t{$dst, $src2}",
|
||||
[(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
|
||||
|
||||
def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
|
||||
"msgfr\t{$dst, $src2}",
|
||||
@ -638,14 +669,18 @@ def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
|
||||
[(SystemZcmp GR64:$src1, i64immSExt32:$src2),
|
||||
(implicit PSW)]>;
|
||||
|
||||
def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
|
||||
"cy\t$src1, $src2",
|
||||
[(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
|
||||
"cg\t$src1, $src2",
|
||||
[(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
|
||||
def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
|
||||
"c\t$src1, $src2",
|
||||
[(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
|
||||
"cy\t$src1, $src2",
|
||||
[(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
|
||||
"cg\t$src1, $src2",
|
||||
[(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
|
||||
def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
|
||||
"clr\t$src1, $src2",
|
||||
@ -662,14 +697,18 @@ def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
|
||||
[(SystemZucmp GR64:$src1, i64immZExt32:$src2),
|
||||
(implicit PSW)]>;
|
||||
|
||||
def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
|
||||
"cly\t$src1, $src2",
|
||||
[(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
|
||||
"clg\t$src1, $src2",
|
||||
[(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
|
||||
"cl\t$src1, $src2",
|
||||
[(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
|
||||
"cly\t$src1, $src2",
|
||||
[(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
|
||||
"clg\t$src1, $src2",
|
||||
[(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
|
||||
(implicit PSW)]>;
|
||||
|
||||
def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
|
||||
"cgfr\t$src1, $src2",
|
||||
|
||||
@ -214,10 +214,14 @@ def i64i32imm : Operand<i64>;
|
||||
// Branch targets have OtherVT type.
|
||||
def brtarget : Operand<OtherVT>;
|
||||
|
||||
// Unigned i12
|
||||
// Unsigned i12
|
||||
def u12imm : Operand<i32> {
|
||||
let PrintMethod = "printU16ImmOperand";
|
||||
let PrintMethod = "printU12ImmOperand";
|
||||
}
|
||||
def u12imm64 : Operand<i64> {
|
||||
let PrintMethod = "printU12ImmOperand";
|
||||
}
|
||||
|
||||
// Signed i16
|
||||
def s16imm : Operand<i32> {
|
||||
let PrintMethod = "printS16ImmOperand";
|
||||
@ -262,8 +266,13 @@ def riaddr : Operand<i64>,
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// rriaddr := reg + reg + imm
|
||||
def rriaddr12 : Operand<i64>,
|
||||
ComplexPattern<i64, 3, "SelectAddrRRI12", [], []> {
|
||||
let PrintMethod = "printRRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, u12imm64:$disp, ADDR64:$index);
|
||||
}
|
||||
def rriaddr : Operand<i64>,
|
||||
ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
|
||||
ComplexPattern<i64, 3, "SelectAddrRRI20", [], []> {
|
||||
let PrintMethod = "printRRIAddrOperand";
|
||||
let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
|
||||
}
|
||||
|
||||
44
test/CodeGen/SystemZ/05-MemLoadsStores.ll
Normal file
44
test/CodeGen/SystemZ/05-MemLoadsStores.ll
Normal file
@ -0,0 +1,44 @@
|
||||
; RUN: llvm-as < %s | llc | grep ly | count 2
|
||||
; RUN: llvm-as < %s | llc | grep sty | count 2
|
||||
; RUN: llvm-as < %s | llc | grep {l.%} | count 2
|
||||
; RUN: llvm-as < %s | llc | grep {st.%} | count 2
|
||||
|
||||
target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
|
||||
target triple = "s390x-linux"
|
||||
|
||||
define void @foo1(i32* nocapture %foo, i32* nocapture %bar) nounwind {
|
||||
entry:
|
||||
%tmp1 = load i32* %foo ; <i32> [#uses=1]
|
||||
store i32 %tmp1, i32* %bar
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo2(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i32* %foo, i64 1 ; <i32*> [#uses=1]
|
||||
%tmp1 = load i32* %add.ptr ; <i32> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %tmp1, i32* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo3(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%sub.ptr = getelementptr i32* %foo, i64 -1 ; <i32*> [#uses=1]
|
||||
%tmp1 = load i32* %sub.ptr ; <i32> [#uses=1]
|
||||
%sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
|
||||
%add.ptr = getelementptr i32* %bar, i64 %sub.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %tmp1, i32* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo4(i32* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i32* %foo, i64 8192 ; <i32*> [#uses=1]
|
||||
%tmp1 = load i32* %add.ptr ; <i32> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %tmp1, i32* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
85
test/CodeGen/SystemZ/05-MemLoadsStores16.ll
Normal file
85
test/CodeGen/SystemZ/05-MemLoadsStores16.ll
Normal file
@ -0,0 +1,85 @@
|
||||
; RUN: llvm-as < %s | llc | grep {sthy.%} | count 2
|
||||
; RUN: llvm-as < %s | llc | grep {lhy.%} | count 2
|
||||
; RUN: llvm-as < %s | llc | grep {lh.%} | count 6
|
||||
; RUN: llvm-as < %s | llc | grep {sth.%} | count 2
|
||||
|
||||
target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
|
||||
target triple = "s390x-linux"
|
||||
|
||||
define void @foo1(i16* nocapture %foo, i16* nocapture %bar) nounwind {
|
||||
entry:
|
||||
%tmp1 = load i16* %foo ; <i16> [#uses=1]
|
||||
store i16 %tmp1, i16* %bar
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo2(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i16* %foo, i64 1 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i16* %bar, i64 %add.ptr3.sum ; <i16*> [#uses=1]
|
||||
store i16 %tmp1, i16* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo3(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%sub.ptr = getelementptr i16* %foo, i64 -1 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %sub.ptr ; <i16> [#uses=1]
|
||||
%sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
|
||||
%add.ptr = getelementptr i16* %bar, i64 %sub.ptr3.sum ; <i16*> [#uses=1]
|
||||
store i16 %tmp1, i16* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo4(i16* nocapture %foo, i16* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i16* %foo, i64 8192 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i16* %bar, i64 %add.ptr3.sum ; <i16*> [#uses=1]
|
||||
store i16 %tmp1, i16* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo5(i16* nocapture %foo, i32* nocapture %bar) nounwind {
|
||||
entry:
|
||||
%tmp1 = load i16* %foo ; <i16> [#uses=1]
|
||||
%conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
|
||||
store i32 %conv, i32* %bar
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo6(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i16* %foo, i64 1 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
|
||||
%conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 1 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %conv, i32* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo7(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%sub.ptr = getelementptr i16* %foo, i64 -1 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %sub.ptr ; <i16> [#uses=1]
|
||||
%conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
|
||||
%sub.ptr3.sum = add i64 %idx, -1 ; <i64> [#uses=1]
|
||||
%add.ptr = getelementptr i32* %bar, i64 %sub.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %conv, i32* %add.ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @foo8(i16* nocapture %foo, i32* nocapture %bar, i64 %idx) nounwind {
|
||||
entry:
|
||||
%add.ptr = getelementptr i16* %foo, i64 8192 ; <i16*> [#uses=1]
|
||||
%tmp1 = load i16* %add.ptr ; <i16> [#uses=1]
|
||||
%conv = sext i16 %tmp1 to i32 ; <i32> [#uses=1]
|
||||
%add.ptr3.sum = add i64 %idx, 8192 ; <i64> [#uses=1]
|
||||
%add.ptr5 = getelementptr i32* %bar, i64 %add.ptr3.sum ; <i32*> [#uses=1]
|
||||
store i32 %conv, i32* %add.ptr5
|
||||
ret void
|
||||
}
|
||||
@ -1,8 +1,8 @@
|
||||
; RUN: llvm-as < %s | llc | not grep aghi
|
||||
; RUN: llvm-as < %s | llc | grep stg | count 1
|
||||
; RUN: llvm-as < %s | llc | grep sty | count 2
|
||||
; RUN: llvm-as < %s | llc | grep sthy | count 2
|
||||
; RUN: llvm-as < %s | llc | grep stcy | count 2
|
||||
; RUN: llvm-as < %s | llc | grep st | count 8
|
||||
; RUN: llvm-as < %s | llc | grep sth | count 2
|
||||
; RUN: llvm-as < %s | llc | grep stc | count 2
|
||||
|
||||
target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
|
||||
target triple = "s390x-unknown-linux-gnu"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user