From 7216920791e3374078bb72c5faf416168eaf042c Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 30 Jul 2009 08:56:19 +0000 Subject: [PATCH] Add a note. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77584 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/X86/README.txt | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/lib/Target/X86/README.txt b/lib/Target/X86/README.txt index 4464878ce21..046d35ce5b6 100644 --- a/lib/Target/X86/README.txt +++ b/lib/Target/X86/README.txt @@ -1932,3 +1932,23 @@ Replacing an icmp+select with a shift should always be considered profitable in instcombine. //===---------------------------------------------------------------------===// + +Re-implement atomic builtins __sync_add_and_fetch() and __sync_sub_and_fetch +properly. + +When the return value is not used (i.e. only care about the value in the +memory), x86 does not have to use add to implement these. Instead, it can use +add, sub, inc, dec instructions with the "lock" prefix. + +This is currently implemented using a bit of instruction selection trick. The +issue is the target independent pattern produces one output and a chain and we +want to map it into one that just output a chain. The current trick is to select +it into a MERGE_VALUES with the first definition being an implicit_def. The +proper solution is to add new ISD opcodes for the no-output variant. DAG +combiner can then transform the node before it gets to target node selection. + +Problem #2 is we are adding a whole bunch of x86 atomic instructions when in +fact these instructions are identical to the non-lock versions. We need a way to +add target specific information to target nodes and have this information +carried over to machine instructions. Asm printer (or JIT) can use this +information to add the "lock" prefix.