6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 18:29:45 +00:00
Code Issues Projects Releases Wiki Activity

Thumb2 parsing and encoding for ADC(register).

Browse Source 
Also add instruction aliases for non-.w versions of SBC since they're the
same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-08-31 18:23:08 +00:00
parent b71541a2db
commit 72335d55d9
2 changed files with 44 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -35,8 +35,9 @@ def t2_so_reg : Operand<i32>, // reg imm
[shl,srl,sra,rotr]> {
let EncoderMethod = "getT2SORegOpValue";
let PrintMethod = "printT2SOOperand";
let MIOperandInfo = (ops rGPR, i32imm);
let DecoderMethod = "DecodeSORegImmOperand";
let ParserMatchClass = ShiftedImmAsmOperand;
let MIOperandInfo = (ops rGPR, i32imm);
}
// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
@ -3490,3 +3491,23 @@ def : T2Pat<(atomic_store_32 t2addrmode_imm8:$addr, GPR:$val),
(t2STRi8 GPR:$val, t2addrmode_imm8:$addr)>;
def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val),
(t2STRs GPR:$val, t2addrmode_so_reg:$addr)>;
//===----------------------------------------------------------------------===//
// Assembler aliases
//
// Aliases for ADC without the ".w" optional width specifier.
def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm",
(t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm",
(t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s)>;
// Aliases for SBC without the ".w" optional width specifier.
def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm",
(t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>;
def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm",
(t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s)>;

22
test/MC/ARM/basic-thumb2-instructions.s
View File

@ -37,6 +37,28 @@ _func:
@ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44]
@ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64]
@------------------------------------------------------------------------------
@ ADC (register)
@------------------------------------------------------------------------------
adc r4, r5, r6
adcs r4, r5, r6
adc.w r9, r1, r3
adcs.w r9, r1, r3
adc r0, r1, r3, ror #4
adcs r0, r1, r3, lsl #7
adc.w r0, r1, r3, lsr #31
adcs.w r0, r1, r3, asr #32
@ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
@ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
@ CHECK: adc.w r9, r1, r3 @ encoding: [0x41,0xeb,0x03,0x09]
@ CHECK: adcs.w r9, r1, r3 @ encoding: [0x51,0xeb,0x03,0x09]
@ CHECK: adc.w r0, r1, r3, ror #4 @ encoding: [0x41,0xeb,0x33,0x10]
@ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10]
@ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70]
@ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00]
@------------------------------------------------------------------------------
@ CBZ/CBNZ
@------------------------------------------------------------------------------