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One more extract_subreg coalescing bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
253945899b
commit
7277a7d031
@ -835,6 +835,19 @@ bool LocalSpiller::PrepForUnfoldOpti(MachineBasicBlock &MBB,
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return false;
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}
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/// findSuperReg - Find the SubReg's super-register of given register class
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/// where its SubIdx sub-register is SubReg.
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static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
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unsigned SubIdx, const MRegisterInfo *MRI) {
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for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
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I != E; ++I) {
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unsigned Reg = *I;
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if (MRI->getSubReg(Reg, SubIdx) == SubReg)
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return Reg;
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}
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return 0;
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}
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/// rewriteMBB - Keep track of which spills are available even after the
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/// register allocator is done with them. If possible, avoid reloading vregs.
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void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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@ -1056,7 +1069,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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<< " instead of reloading into same physreg.\n";
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unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
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MI.getOperand(i).setReg(RReg);
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ReusedOperands.markClobbered(PhysReg);
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ReusedOperands.markClobbered(RReg);
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++NumReused;
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continue;
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}
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@ -1295,6 +1308,13 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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continue;
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}
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unsigned SubIdx = 0;
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bool isSubReg = RegMap->isSubRegister(VirtReg);
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if (isSubReg) {
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SubIdx = RegMap->getSubRegisterIndex(VirtReg);
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VirtReg = RegMap->getSuperRegister(VirtReg);
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}
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bool DoReMat = VRM.isReMaterialized(VirtReg);
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if (DoReMat)
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ReMatDefs.insert(&MI);
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@ -1307,9 +1327,15 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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// the store from the correct physical register.
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unsigned PhysReg;
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int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
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if (TiedOp != -1)
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if (TiedOp != -1) {
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PhysReg = MI.getOperand(TiedOp).getReg();
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else {
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if (isSubReg) {
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unsigned SuperReg = findSuperReg(RC, PhysReg, SubIdx, MRI);
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assert(SuperReg && MRI->getSubReg(SuperReg, SubIdx) == PhysReg &&
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"Can't find corresponding super-register!");
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PhysReg = SuperReg;
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}
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} else {
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PhysReg = VRM.getPhys(VirtReg);
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if (ReusedOperands.isClobbered(PhysReg)) {
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// Another def has taken the assigned physreg. It must have been a
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@ -1320,8 +1346,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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}
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MF.setPhysRegUsed(PhysReg);
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ReusedOperands.markClobbered(PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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unsigned RReg = isSubReg ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
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ReusedOperands.markClobbered(RReg);
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MI.getOperand(i).setReg(RReg);
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if (!MO.isDead()) {
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MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
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DOUT << "Store:\t" << *next(MII);
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144
test/CodeGen/X86/2007-11-02-BadAsm.ll
Normal file
144
test/CodeGen/X86/2007-11-02-BadAsm.ll
Normal file
@ -0,0 +1,144 @@
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; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl | not grep rax
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%struct.color_sample = type { i64 }
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%struct.gs_matrix = type { float, i64, float, i64, float, i64, float, i64, float, i64, float, i64 }
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%struct.ref = type { %struct.color_sample, i16, i16 }
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%struct.status = type { %struct.gs_matrix, i8*, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32 }
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define i32 @ztype1imagepath(%struct.ref* %op) {
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entry:
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br i1 false, label %cond_next, label %UnifiedReturnBlock
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cond_next: ; preds = %entry
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br i1 false, label %cond_next68, label %UnifiedReturnBlock
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cond_next68: ; preds = %cond_next
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%tmp5.i.i = malloc i8, i32 0 ; <i8*> [#uses=2]
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br i1 false, label %bb81.outer.i, label %xit.i
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bb81.outer.i: ; preds = %bb87.i, %cond_next68
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%tmp67.i = add i32 0, 1 ; <i32> [#uses=1]
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br label %bb81.i
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bb61.i: ; preds = %bb81.i
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%tmp71.i = getelementptr i8* %tmp5.i.i, i64 0 ; <i8*> [#uses=1]
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%tmp72.i = load i8* %tmp71.i, align 1 ; <i8> [#uses=1]
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%tmp73.i = icmp eq i8 %tmp72.i, 0 ; <i1> [#uses=1]
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br i1 %tmp73.i, label %bb81.i, label %xit.i
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bb81.i: ; preds = %bb61.i, %bb81.outer.i
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br i1 false, label %bb87.i, label %bb61.i
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bb87.i: ; preds = %bb81.i
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br i1 false, label %bb81.outer.i, label %xit.i
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xit.i: ; preds = %bb87.i, %bb61.i, %cond_next68
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%lsbx.0.reg2mem.1.i = phi i32 [ 0, %cond_next68 ], [ 0, %bb61.i ], [ %tmp67.i, %bb87.i ] ; <i32> [#uses=1]
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%tmp6162.i.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1]
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%tmp67.i15.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1]
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%tmp24.i27.i = icmp eq i64 0, 0 ; <i1> [#uses=1]
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br i1 %tmp24.i27.i, label %cond_next.i79.i, label %cond_true.i34.i
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cond_true.i34.i: ; preds = %xit.i
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ret i32 0
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cond_next.i79.i: ; preds = %xit.i
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%phitmp167.i = fptosi double 0.000000e+00 to i64 ; <i64> [#uses=1]
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%tmp142143.i = fpext float %tmp6162.i.i to double ; <double> [#uses=1]
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%tmp2.i139.i = add double %tmp142143.i, 5.000000e-01 ; <double> [#uses=1]
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%tmp23.i140.i = fptosi double %tmp2.i139.i to i64 ; <i64> [#uses=1]
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br i1 false, label %cond_true.i143.i, label %round_coord.exit148.i
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cond_true.i143.i: ; preds = %cond_next.i79.i
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%tmp8.i142.i = icmp sgt i64 %tmp23.i140.i, -32768 ; <i1> [#uses=1]
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br i1 %tmp8.i142.i, label %cond_true11.i145.i, label %round_coord.exit148.i
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cond_true11.i145.i: ; preds = %cond_true.i143.i
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ret i32 0
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round_coord.exit148.i: ; preds = %cond_true.i143.i, %cond_next.i79.i
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%tmp144149.i = phi i32 [ 32767, %cond_next.i79.i ], [ -32767, %cond_true.i143.i ] ; <i32> [#uses=1]
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store i32 %tmp144149.i, i32* null, align 8
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%tmp147148.i = fpext float %tmp67.i15.i to double ; <double> [#uses=1]
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%tmp2.i128.i = add double %tmp147148.i, 5.000000e-01 ; <double> [#uses=1]
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%tmp23.i129.i = fptosi double %tmp2.i128.i to i64 ; <i64> [#uses=2]
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%tmp5.i130.i = icmp slt i64 %tmp23.i129.i, 32768 ; <i1> [#uses=1]
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br i1 %tmp5.i130.i, label %cond_true.i132.i, label %round_coord.exit137.i
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cond_true.i132.i: ; preds = %round_coord.exit148.i
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%tmp8.i131.i = icmp sgt i64 %tmp23.i129.i, -32768 ; <i1> [#uses=1]
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br i1 %tmp8.i131.i, label %cond_true11.i134.i, label %round_coord.exit137.i
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cond_true11.i134.i: ; preds = %cond_true.i132.i
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br label %round_coord.exit137.i
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round_coord.exit137.i: ; preds = %cond_true11.i134.i, %cond_true.i132.i, %round_coord.exit148.i
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%tmp149138.i = phi i32 [ 0, %cond_true11.i134.i ], [ 32767, %round_coord.exit148.i ], [ -32767, %cond_true.i132.i ] ; <i32> [#uses=1]
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br i1 false, label %cond_true.i121.i, label %round_coord.exit126.i
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cond_true.i121.i: ; preds = %round_coord.exit137.i
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br i1 false, label %cond_true11.i123.i, label %round_coord.exit126.i
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cond_true11.i123.i: ; preds = %cond_true.i121.i
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br label %round_coord.exit126.i
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round_coord.exit126.i: ; preds = %cond_true11.i123.i, %cond_true.i121.i, %round_coord.exit137.i
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%tmp153127.i = phi i32 [ 0, %cond_true11.i123.i ], [ 32767, %round_coord.exit137.i ], [ -32767, %cond_true.i121.i ] ; <i32> [#uses=1]
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br i1 false, label %cond_true.i110.i, label %round_coord.exit115.i
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cond_true.i110.i: ; preds = %round_coord.exit126.i
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br i1 false, label %cond_true11.i112.i, label %round_coord.exit115.i
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cond_true11.i112.i: ; preds = %cond_true.i110.i
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br label %round_coord.exit115.i
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round_coord.exit115.i: ; preds = %cond_true11.i112.i, %cond_true.i110.i, %round_coord.exit126.i
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%tmp157116.i = phi i32 [ 0, %cond_true11.i112.i ], [ 32767, %round_coord.exit126.i ], [ -32767, %cond_true.i110.i ] ; <i32> [#uses=2]
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br i1 false, label %cond_true.i99.i, label %round_coord.exit104.i
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cond_true.i99.i: ; preds = %round_coord.exit115.i
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br i1 false, label %cond_true11.i101.i, label %round_coord.exit104.i
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cond_true11.i101.i: ; preds = %cond_true.i99.i
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%tmp1213.i100.i = trunc i64 %phitmp167.i to i32 ; <i32> [#uses=1]
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br label %cond_next172.i
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round_coord.exit104.i: ; preds = %cond_true.i99.i, %round_coord.exit115.i
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%UnifiedRetVal.i102.i = phi i32 [ 32767, %round_coord.exit115.i ], [ -32767, %cond_true.i99.i ] ; <i32> [#uses=1]
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%tmp164.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp157116.i ) ; <i32> [#uses=0]
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br label %cond_next172.i
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cond_next172.i: ; preds = %round_coord.exit104.i, %cond_true11.i101.i
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%tmp161105.reg2mem.0.i = phi i32 [ %tmp1213.i100.i, %cond_true11.i101.i ], [ %UnifiedRetVal.i102.i, %round_coord.exit104.i ] ; <i32> [#uses=1]
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%tmp174.i = icmp eq i32 %tmp153127.i, 0 ; <i1> [#uses=1]
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%bothcond.i = and i1 false, %tmp174.i ; <i1> [#uses=1]
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%tmp235.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp149138.i ) ; <i32> [#uses=0]
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%tmp245.i = load i8** null, align 8 ; <i8*> [#uses=2]
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%tmp246.i = getelementptr i8* %tmp245.i, i64 1 ; <i8*> [#uses=1]
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br i1 %bothcond.i, label %cond_next254.i, label %bb259.i
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cond_next254.i: ; preds = %cond_next172.i
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store i8 13, i8* %tmp245.i, align 1
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br label %bb259.i
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bb259.i: ; preds = %cond_next254.i, %cond_next172.i
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%storemerge.i = phi i8* [ %tmp246.i, %cond_next254.i ], [ null, %cond_next172.i ] ; <i8*> [#uses=0]
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%tmp261.i = shl i32 %lsbx.0.reg2mem.1.i, 2 ; <i32> [#uses=1]
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store i32 %tmp261.i, i32* null, align 8
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%tmp270.i = add i32 0, %tmp157116.i ; <i32> [#uses=1]
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store i32 %tmp270.i, i32* null, align 8
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%tmp275.i = add i32 0, %tmp161105.reg2mem.0.i ; <i32> [#uses=0]
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br i1 false, label %trace_cells.exit.i, label %bb.preheader.i.i
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bb.preheader.i.i: ; preds = %bb259.i
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ret i32 0
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trace_cells.exit.i: ; preds = %bb259.i
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free i8* %tmp5.i.i
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ret i32 0
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UnifiedReturnBlock: ; preds = %cond_next, %entry
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ret i32 -20
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}
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declare fastcc i32 @put_int(%struct.status*, i32)
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