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Remove unused bitvectors that record ARM callee-saved registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125534 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-02-14 23:40:38 +00:00
parent eb9f040f0d
commit 727961a1a3
2 changed files with 0 additions and 23 deletions
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6
lib/Target/ARM/ARMFrameLowering.cpp
View File

@ -833,7 +833,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
unsigned Reg = CSRegs[i];
bool Spilled = false;
if (MF.getRegInfo().isPhysRegUsed(Reg)) {
AFI->setCSRegisterIsSpilled(Reg);
Spilled = true;
CanEliminateFrame = false;
} else {
@ -932,7 +931,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
// Spill LR as well so we can fold BX_RET to the registers restore (LDM).
if (!LRSpilled && CS1Spilled) {
MF.getRegInfo().setPhysRegUsed(ARM::LR);
AFI->setCSRegisterIsSpilled(ARM::LR);
NumGPRSpills++;
UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
@ -957,7 +955,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (!AFI->isThumb1OnlyFunction() ||
isARMLowRegister(Reg) || Reg == ARM::LR) {
MF.getRegInfo().setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!RegInfo->isReservedReg(MF, Reg))
ExtraCSSpill = true;
break;
@ -966,7 +963,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
} else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) {
unsigned Reg = UnspilledCS2GPRs.front();
MF.getRegInfo().setPhysRegUsed(Reg);
AFI->setCSRegisterIsSpilled(Reg);
if (!RegInfo->isReservedReg(MF, Reg))
ExtraCSSpill = true;
}
@ -1006,7 +1002,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (Extras.size() && NumExtras == 0) {
for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
MF.getRegInfo().setPhysRegUsed(Extras[i]);
AFI->setCSRegisterIsSpilled(Extras[i]);
}
} else if (!AFI->isThumb1OnlyFunction()) {
// note: Thumb1 functions spill to R12, not the stack. Reserve a slot
@ -1021,7 +1016,6 @@ ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
if (ForceLRSpill) {
MF.getRegInfo().setPhysRegUsed(ARM::LR);
AFI->setCSRegisterIsSpilled(ARM::LR);
AFI->setLRIsSpilledForFarJump(true);
}
}

17
lib/Target/ARM/ARMMachineFunctionInfo.h
View File

@ -79,10 +79,6 @@ class ARMFunctionInfo : public MachineFunctionInfo {
BitVector GPRCS2Frames;
BitVector DPRCSFrames;
/// SpilledCSRegs - A BitVector mask of all spilled callee-saved registers.
///
BitVector SpilledCSRegs;
/// JumpTableUId - Unique id for jumptables.
///
unsigned JumpTableUId;
@ -119,7 +115,6 @@ public:
FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
GPRCS1Size(0), GPRCS2Size(0), DPRCSSize(0),
GPRCS1Frames(32), GPRCS2Frames(32), DPRCSFrames(32),
SpilledCSRegs(MF.getTarget().getRegisterInfo()->getNumRegs()),
JumpTableUId(0), PICLabelUId(0),
VarArgsFrameIndex(0), HasITBlocks(false) {}
@ -211,18 +206,6 @@ public:
}
}
void setCSRegisterIsSpilled(unsigned Reg) {
SpilledCSRegs.set(Reg);
}
bool isCSRegisterSpilled(unsigned Reg) const {
return SpilledCSRegs[Reg];
}
const BitVector &getSpilledCSRegisters() const {
return SpilledCSRegs;
}
unsigned createJumpTableUId() {
return JumpTableUId++;
}