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Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -5634,6 +5634,7 @@ multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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// extload, zextload and sextload for a lengthening load followed by another
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// extload, zextload and sextload for a lengthening load followed by another
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// lengthening load, to quadruple the initial length.
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// lengthening load, to quadruple the initial length.
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//
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv4i32
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@ -5644,28 +5645,63 @@ multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
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// qsub_0)>;
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// qsub_0)>;
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multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty, SubRegIndex RegType> {
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string Insn2Ty> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0))>;
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}
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// extload, zextload and sextload for a lengthening load followed by another
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// lengthening load, to quadruple the initial length, but which ends up only
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// requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
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//
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// Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
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// Pat<(v4i32 (extloadvi8 addrmode5:$addr))
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// (EXTRACT_SUBREG (VMOVLuv4i32
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// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
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// (VLDRS addrmode5:$addr),
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// ssub_0)),
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// dsub_0)),
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// dsub_0)>;
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multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
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string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
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string Insn2Ty> {
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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ssub_0)), dsub_0)),
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RegType)>;
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dsub_0)>;
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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ssub_0)), dsub_0)),
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RegType)>;
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dsub_0)>;
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)),
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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(INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr),
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ssub_0)), dsub_0)),
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ssub_0)), dsub_0)),
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RegType)>;
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dsub_0)>;
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}
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}
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defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
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defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16
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@ -5677,11 +5713,11 @@ defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16
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defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
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defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
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// Double lengthening - v4i8 -> v4i16 -> v4i32
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// Double lengthening - v4i8 -> v4i16 -> v4i32
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defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0>;
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defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
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// v2i8 -> v2i16 -> v2i32
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// v2i8 -> v2i16 -> v2i32
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defm : Lengthen_Double<"2", "i32", "i8", "8", "i16", "4", "i32", dsub_0>;
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defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
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// v2i16 -> v2i32 -> v2i64
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// v2i16 -> v2i32 -> v2i64
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defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64", qsub_0>;
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defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
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// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
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// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
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def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
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def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)),
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@ -44,3 +44,17 @@ define <4 x i8> @h(<4 x float> %v) {
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%1 = fptoui <4 x float> %v to <4 x i8>
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%1 = fptoui <4 x float> %v to <4 x i8>
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ret <4 x i8> %1
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ret <4 x i8> %1
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}
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}
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; CHECK: i:
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define <4 x i8> @i(<4 x i8>* %x) {
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; CHECK: vldr
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; CHECK: vmovl.s8
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; CHECK: vmovl.s16
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; CHECK: vrecpe
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; CHECK: vrecps
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; CHECK: vmul
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; CHECK: vmovn
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%1 = load <4 x i8>* %x, align 4
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%2 = sdiv <4 x i8> zeroinitializer, %1
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ret <4 x i8> %2
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}
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