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VFP/NEON load/store multiple instructions are addrmode4, not 5.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113322 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-09-08 00:25:50 +00:00
parent e9f1882406
commit 72db182438
3 changed files with 14 additions and 14 deletions
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8
lib/Target/ARM/ARMInstrFormats.td
View File

@ -1332,9 +1332,9 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
}
// Load / store multiple
class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
VFPLdStMulFrm, itin, asm, cstr, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
let Inst{27-25} = 0b110;
@ -1344,9 +1344,9 @@ class AXDI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
let D = VFPNeonDomain;
}
class AXSI5<dag oops, dag iops, IndexMode im, InstrItinClass itin,
class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
string asm, string cstr, list<dag> pattern>
: VFPXI<oops, iops, AddrMode5, Size4Bytes, im,
: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
VFPLdStMulFrm, itin, asm, cstr, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info.
let Inst{27-25} = 0b110;

4
lib/Target/ARM/ARMInstrNEON.td
View File

@ -133,7 +133,7 @@ def nModImm : Operand<i32> {
// This is equivalent to VLDMD except that it has a Q register operand
// instead of a pair of D registers.
def VLDMQ
: AXDI5<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
: AXDI4<(outs QPR:$dst), (ins addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, ${dst:dregpair}", "",
[(set QPR:$dst, (v2f64 (load addrmode4:$addr)))]>;
@ -151,7 +151,7 @@ def VLD1q
// This is equivalent to VSTMD except that it has a Q register operand
// instead of a pair of D registers.
def VSTMQ
: AXDI5<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
: AXDI4<(outs), (ins QPR:$src, addrmode4:$addr, pred:$p),
IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, ${src:dregpair}", "",
[(store (v2f64 QPR:$src), addrmode4:$addr)]>;

16
lib/Target/ARM/ARMInstrVFP.td
View File

@ -77,19 +77,19 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
//
let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
def VLDMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
def VLDMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
variable_ops), IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
let Inst{20} = 1;
}
def VLDMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
def VLDMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$dsts,
variable_ops), IndexModeNone, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr, $dsts", "", []> {
let Inst{20} = 1;
}
def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
def VLDMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr!, $dsts",
@ -97,7 +97,7 @@ def VLDMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
let Inst{20} = 1;
}
def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
def VLDMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$dsts, variable_ops),
IndexModeUpd, IIC_fpLoadm,
"vldm${addr:submode}${p}\t$addr!, $dsts",
@ -107,19 +107,19 @@ def VLDMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
} // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq
let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
def VSTMD : AXDI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
def VSTMD : AXDI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
variable_ops), IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
let Inst{20} = 0;
}
def VSTMS : AXSI5<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
def VSTMS : AXSI4<(outs), (ins addrmode4:$addr, pred:$p, reglist:$srcs,
variable_ops), IndexModeNone, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr, $srcs", "", []> {
let Inst{20} = 0;
}
def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
def VSTMD_UPD : AXDI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr!, $srcs",
@ -127,7 +127,7 @@ def VSTMD_UPD : AXDI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
let Inst{20} = 0;
}
def VSTMS_UPD : AXSI5<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
reglist:$srcs, variable_ops),
IndexModeUpd, IIC_fpStorem,
"vstm${addr:submode}${p}\t$addr!, $srcs",