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Enable -schedmodel, but prefer itineraries until we have more benchmark data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165188 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -21,7 +21,7 @@
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using namespace llvm;
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using namespace llvm;
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static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(false),
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static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
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cl::desc("Use TargetSchedModel for latency lookup"));
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cl::desc("Use TargetSchedModel for latency lookup"));
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static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
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static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
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@ -123,60 +123,59 @@ unsigned TargetSchedModel::computeOperandLatency(
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if (DefLatency >= 0)
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if (DefLatency >= 0)
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return DefLatency;
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return DefLatency;
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if (!FindMin && EnableSchedModel && hasInstrSchedModel()) {
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if (EnableSchedItins && hasInstrItineraries()) {
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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int OperLatency = 0;
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unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
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if (UseMI) {
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if (DefIdx < SCDesc->NumWriteLatencyEntries) {
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OperLatency =
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// Lookup the definition's write latency in SubtargetInfo.
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TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
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const MCWriteLatencyEntry *WLEntry =
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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unsigned WriteID = WLEntry->WriteResourceID;
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unsigned Latency = WLEntry->Cycles;
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if (!UseMI)
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return Latency;
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// Lookup the use's latency adjustment in SubtargetInfo.
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const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
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if (UseDesc->NumReadAdvanceEntries == 0)
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return Latency;
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unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
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return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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}
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}
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// If DefIdx does not exist in the model (e.g. implicit defs), then return
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else {
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// unit latency (defaultDefLatency may be too conservative).
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unsigned DefClass = DefMI->getDesc().getSchedClass();
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OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
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}
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if (OperLatency >= 0)
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return OperLatency;
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// No operand latency was found.
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unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
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// Expected latency is the max of the stage latency and itinerary props.
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if (!FindMin)
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InstrLatency = std::max(InstrLatency,
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TII->defaultDefLatency(&SchedModel, DefMI));
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return InstrLatency;
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}
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assert(!FindMin && EnableSchedModel && hasInstrSchedModel() &&
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"Expected a SchedModel for this cpu");
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const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
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unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
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if (DefIdx < SCDesc->NumWriteLatencyEntries) {
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// Lookup the definition's write latency in SubtargetInfo.
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const MCWriteLatencyEntry *WLEntry =
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STI->getWriteLatencyEntry(SCDesc, DefIdx);
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unsigned WriteID = WLEntry->WriteResourceID;
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unsigned Latency = WLEntry->Cycles;
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if (!UseMI)
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return Latency;
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// Lookup the use's latency adjustment in SubtargetInfo.
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const MCSchedClassDesc *UseDesc = resolveSchedClass(UseMI);
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if (UseDesc->NumReadAdvanceEntries == 0)
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return Latency;
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unsigned UseIdx = findUseIdx(UseMI, UseOperIdx);
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return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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}
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// If DefIdx does not exist in the model (e.g. implicit defs), then return
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// unit latency (defaultDefLatency may be too conservative).
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#ifndef NDEBUG
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#ifndef NDEBUG
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if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
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if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit()
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&& !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
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&& !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef()) {
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std::string Err;
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std::string Err;
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raw_string_ostream ss(Err);
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raw_string_ostream ss(Err);
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ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
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ss << "DefIdx " << DefIdx << " exceeds machine model writes for "
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<< *DefMI;
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<< *DefMI;
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report_fatal_error(ss.str());
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report_fatal_error(ss.str());
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}
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}
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#endif
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#endif
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return 1;
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return 1;
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}
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assert(EnableSchedItins && hasInstrItineraries() &&
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"operand latency requires itinerary");
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int OperLatency = 0;
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if (UseMI) {
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OperLatency =
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TII->getOperandLatency(&InstrItins, DefMI, DefOperIdx, UseMI, UseOperIdx);
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}
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else {
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unsigned DefClass = DefMI->getDesc().getSchedClass();
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OperLatency = InstrItins.getOperandCycle(DefClass, DefOperIdx);
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}
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if (OperLatency >= 0)
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return OperLatency;
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// No operand latency was found.
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unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
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// Expected latency is the max of the stage latency and itinerary props.
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if (!FindMin)
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InstrLatency = std::max(InstrLatency,
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TII->defaultDefLatency(&SchedModel, DefMI));
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return InstrLatency;
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}
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}
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