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reenable collapse of loadimm+AND -> dep.z (thanks guys)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22944 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duraid Madina 2005-08-21 15:43:53 +00:00
parent fe0c2c8721
commit 7340dd5d2e
1 changed files with 6 additions and 5 deletions
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11
lib/Target/IA64/IA64ISelPattern.cpp
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@ -1439,7 +1439,7 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
case MVT::i32:
case MVT::i64: {
Tmp1 = SelectExpr(N.getOperand(0));
/* FIXME switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
case 1: // ANDing a constant that is 2^n-1 for some n
switch (Tmp3) {
case 8: // if AND 0x00000000000000FF, be quaint and use zxt1
@ -1452,12 +1452,13 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n");
BuildMI(BB, IA64::ZXT4, 1, Result).addReg(Tmp1);
break;
default: // otherwise, use dep.z to paste zeros
BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
// FIXME: assert the dep.z is in bounds
BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
.addImm(0).addImm(Tmp3);
break;
}
return Result; // early exit
FIXME } */ // fallthrough and emit a simple AND:
}
return Result; // early exit
} // fallthrough and emit a simple AND:
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
}