mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
operand of a conditional branch to allow load folding into CMP / TEST instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30241 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
019f851ab2
commit
734503be59
@ -3394,9 +3394,9 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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SDOperand ShOpLo = Op.getOperand(0);
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SDOperand ShOpHi = Op.getOperand(1);
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SDOperand ShAmt = Op.getOperand(2);
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SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
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DAG.getConstant(31, MVT::i8))
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: DAG.getConstant(0, MVT::i32);
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SDOperand Tmp1 = isSRA ?
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DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
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DAG.getConstant(0, MVT::i32);
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SDOperand Tmp2, Tmp3;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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@ -3407,25 +3407,23 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
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}
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SDOperand InFlag =
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DAG.getNode(X86ISD::CMP, MVT::Flag,
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DAG.getNode(ISD::AND, MVT::i8,
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ShAmt, DAG.getConstant(32, MVT::i8)),
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DAG.getConstant(0, MVT::i8));
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
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DAG.getConstant(32, MVT::i8));
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SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
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SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(MVT::i32);
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Tys.push_back(MVT::Flag);
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std::vector<SDOperand> Ops;
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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if (Op.getOpcode() == ISD::SHL_PARTS) {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(InFlag);
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Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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InFlag = Hi.getValue(1);
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Ops.clear();
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@ -3433,13 +3431,13 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(InFlag);
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Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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} else {
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Ops.push_back(Tmp2);
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Ops.push_back(Tmp3);
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Ops.push_back(CC);
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Ops.push_back(InFlag);
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Lo = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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InFlag = Lo.getValue(1);
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Ops.clear();
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@ -3447,16 +3445,14 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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Ops.push_back(Tmp1);
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Ops.push_back(CC);
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Ops.push_back(InFlag);
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Hi = DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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}
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Tys.clear();
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Tys.push_back(MVT::i32);
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Tys.push_back(MVT::i32);
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VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
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Ops.clear();
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Ops.push_back(Lo);
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Ops.push_back(Hi);
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return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
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return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
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@ -3613,163 +3609,139 @@ SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
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}
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SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
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SDOperand Chain) {
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assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
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SDOperand Cond;
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Op1 = Op.getOperand(1);
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SDOperand CC = Op.getOperand(2);
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
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bool Flip;
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unsigned X86CC;
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VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
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if (translateX86CC(CC, isFP, X86CC, Flip)) {
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if (Flip)
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Op.getOperand(1), Op.getOperand(0));
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else
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Op.getOperand(0), Op.getOperand(1));
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return DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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} else {
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if (Flip) std::swap(Op0, Op1);
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SDOperand Ops1[] = { Chain, Op0, Op1 };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops1, 3).getValue(1);
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SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
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return DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
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}
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assert(isFP && "Illegal integer SetCC!");
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
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Op.getOperand(0), Op.getOperand(1));
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std::vector<MVT::ValueType> Tys;
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std::vector<SDOperand> Ops;
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SDOperand COps[] = { Chain, Op0, Op1 };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
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switch (SetCCOpcode) {
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default: assert(false && "Illegal floating point SetCC!");
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case ISD::SETOEQ: { // !PF & ZF
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Tys.push_back(MVT::i8);
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Tys.push_back(MVT::Flag);
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Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
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Ops.push_back(Cond);
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86ISD::COND_E, MVT::i8),
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Tmp1.getValue(1));
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SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_NP, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_E, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
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return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
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}
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case ISD::SETUNE: { // PF | !ZF
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Tys.push_back(MVT::i8);
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Tys.push_back(MVT::Flag);
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Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
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Ops.push_back(Cond);
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86ISD::COND_NE, MVT::i8),
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Tmp1.getValue(1));
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SDOperand Ops1[] = { DAG.getConstant(X86ISD::COND_P, MVT::i8), Cond };
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SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops1, 2);
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SDOperand Ops2[] = { DAG.getConstant(X86ISD::COND_NE, MVT::i8),
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Tmp1.getValue(1) };
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SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
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return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
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}
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}
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}
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}
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SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType VT = Op.getValueType();
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bool isFPStack = MVT::isFloatingPoint(VT) && !X86ScalarSSE;
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bool addTest = false;
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Cond, CC;
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if (Op0.getOpcode() == ISD::SETCC)
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Op0 = LowerOperation(Op0, DAG);
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bool addTest = true;
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SDOperand Chain = DAG.getEntryNode();
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SDOperand Cond = Op.getOperand(0);
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SDOperand CC;
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerSETCC(Cond, DAG, Chain);
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if (Cond.getOpcode() == X86ISD::SETCC) {
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CC = Cond.getOperand(0);
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if (Op0.getOpcode() == X86ISD::SETCC) {
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). If the X86ISD::SETCC does not
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// have another use it will be eliminated.
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// If the X86ISD::SETCC has more than one use, then it's probably better
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// (since flag operand cannot be shared). Use it as the condition setting
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// operand in place of the X86ISD::SETCC.
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// If the X86ISD::SETCC has more than one use, then perhaps it's better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason).
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unsigned CmpOpc = Op0.getOperand(1).getOpcode();
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if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
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CmpOpc == X86ISD::UCOMI) {
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if (!Op0.hasOneUse()) {
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std::vector<MVT::ValueType> Tys;
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for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
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Tys.push_back(Op0.Val->getValueType(i));
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std::vector<SDOperand> Ops;
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for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
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Ops.push_back(Op0.getOperand(i));
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Op0 = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
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// pressure reason)?
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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bool IllegalFPCMov = !X86ScalarSSE &&
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MVT::isFloatingPoint(Op.getValueType()) &&
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!hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
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!IllegalFPCMov) {
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SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
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Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
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addTest = false;
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}
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}
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CC = Op0.getOperand(0);
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Cond = Op0.getOperand(1);
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// Make a copy as flag result cannot be used by more than one.
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Cond = DAG.getNode(CmpOpc, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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addTest =
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isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
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} else
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addTest = true;
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} else
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addTest = true;
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Op0,
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DAG.getConstant(0, MVT::i8));
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SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
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}
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std::vector<MVT::ValueType> Tys;
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Tys.push_back(Op.getValueType());
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Tys.push_back(MVT::Flag);
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std::vector<SDOperand> Ops;
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VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
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SmallVector<SDOperand, 4> Ops;
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// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
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// condition is true.
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Ops.push_back(Op.getOperand(2));
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Ops.push_back(Op.getOperand(1));
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Ops.push_back(CC);
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Ops.push_back(Cond);
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return DAG.getNode(X86ISD::CMOV, Tys, &Ops[0], Ops.size());
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Ops.push_back(Cond.getValue(1));
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return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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}
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SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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bool addTest = false;
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bool addTest = true;
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SDOperand Chain = Op.getOperand(0);
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SDOperand Cond = Op.getOperand(1);
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SDOperand Dest = Op.getOperand(2);
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SDOperand CC;
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
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if (Cond.getOpcode() == ISD::SETCC)
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Cond = LowerOperation(Cond, DAG);
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Cond = LowerSETCC(Cond, DAG, Chain);
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if (Cond.getOpcode() == X86ISD::SETCC) {
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). If the X86ISD::SETCC does not
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// have another use it will be eliminated.
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// If the X86ISD::SETCC has more than one use, then it's probably better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason).
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unsigned CmpOpc = Cond.getOperand(1).getOpcode();
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if (CmpOpc == X86ISD::CMP || CmpOpc == X86ISD::COMI ||
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CmpOpc == X86ISD::UCOMI) {
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if (!Cond.hasOneUse()) {
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std::vector<MVT::ValueType> Tys;
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for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
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Tys.push_back(Cond.Val->getValueType(i));
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std::vector<SDOperand> Ops;
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for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
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Ops.push_back(Cond.getOperand(i));
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Cond = DAG.getNode(X86ISD::SETCC, Tys, &Ops[0], Ops.size());
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}
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CC = Cond.getOperand(0);
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Cond = Cond.getOperand(1);
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// Make a copy as flag result cannot be used by more than one.
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Cond = DAG.getNode(CmpOpc, MVT::Flag,
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Cond.getOperand(0), Cond.getOperand(1));
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} else
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addTest = true;
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} else
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addTest = true;
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// If condition flag is set by a X86ISD::CMP, then make a copy of it
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// (since flag operand cannot be shared). Use it as the condition setting
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// operand in place of the X86ISD::SETCC.
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// If the X86ISD::SETCC has more than one use, then perhaps it's better
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// to use a test instead of duplicating the X86ISD::CMP (for register
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// pressure reason)?
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SDOperand Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
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SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
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Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
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addTest = false;
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}
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}
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Cond,
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DAG.getConstant(0, MVT::i8));
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SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
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Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
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}
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return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Op.getOperand(0), Op.getOperand(2), CC, Cond);
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Cond, Op.getOperand(2), CC, Cond.getValue(1));
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}
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SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
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@ -4382,13 +4354,18 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
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CC = ISD::SETNE;
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break;
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}
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bool Flip;
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unsigned X86CC;
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translateX86CC(CC, true, X86CC, Flip);
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SDOperand Cond = DAG.getNode(Opc, MVT::Flag, Op.getOperand(Flip?2:1),
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Op.getOperand(Flip?1:2));
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SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
|
||||
|
||||
const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
|
||||
SDOperand Ops1[] = { DAG.getEntryNode(), Op.getOperand(Flip?2:1),
|
||||
Op.getOperand(Flip?1:2) };
|
||||
SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
|
||||
VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
|
||||
SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
|
||||
SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
|
||||
return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
|
||||
}
|
||||
}
|
||||
@ -4414,7 +4391,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
||||
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
||||
case ISD::FABS: return LowerFABS(Op, DAG);
|
||||
case ISD::FNEG: return LowerFNEG(Op, DAG);
|
||||
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
||||
case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
|
||||
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
||||
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
||||
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
||||
|
||||
@ -381,7 +381,7 @@ namespace llvm {
|
||||
SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerFABS(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG, SDOperand Chain);
|
||||
SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
|
||||
SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
|
||||
|
||||
@ -51,7 +51,7 @@ def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>;
|
||||
def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
|
||||
|
||||
def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
|
||||
[SDNPOutFlag]>;
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
|
||||
def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
|
||||
[SDNPInFlag, SDNPOutFlag]>;
|
||||
@ -2093,18 +2093,17 @@ def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
|
||||
"test{l} {$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
|
||||
}
|
||||
// FIXME: These patterns are disabled until isel issue surrounding
|
||||
//CodeGen/X86/test-load-fold.ll is fixed.
|
||||
|
||||
def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
|
||||
"test{b} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)*/]>;
|
||||
[(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)]>;
|
||||
def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
|
||||
"test{w} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)*/]>,
|
||||
[(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)]>,
|
||||
OpSize;
|
||||
def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
|
||||
"test{l} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)*/]>;
|
||||
[(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)]>;
|
||||
|
||||
def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
|
||||
(ops GR8:$src1, i8imm:$src2),
|
||||
@ -2118,21 +2117,20 @@ def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
|
||||
(ops GR32:$src1, i32imm:$src2),
|
||||
"test{l} {$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
|
||||
// FIXME: These patterns are disabled until isel issue surrounding
|
||||
//CodeGen/X86/test-load-fold.ll is fixed.
|
||||
|
||||
def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
|
||||
(ops i8mem:$src1, i8imm:$src2),
|
||||
"test{b} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)*/]>;
|
||||
[(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)]>;
|
||||
def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
|
||||
(ops i16mem:$src1, i16imm:$src2),
|
||||
"test{w} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)*/]>,
|
||||
[(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)]>,
|
||||
OpSize;
|
||||
def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
|
||||
(ops i32mem:$src1, i32imm:$src2),
|
||||
"test{l} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)*/]>;
|
||||
[(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)]>;
|
||||
|
||||
|
||||
// Condition code ops, incl. set if equal/not equal/...
|
||||
|
||||
@ -26,9 +26,9 @@ def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
|
||||
def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
|
||||
[SDNPCommutative, SDNPAssociative]>;
|
||||
def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
|
||||
[SDNPOutFlag]>;
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
|
||||
[SDNPOutFlag]>;
|
||||
[SDNPHasChain, SDNPOutFlag]>;
|
||||
def X86s2vec : SDNode<"X86ISD::S2VEC",
|
||||
SDTypeProfile<1, 1, []>, []>;
|
||||
def X86pextrw : SDNode<"X86ISD::PEXTRW",
|
||||
|
||||
@ -711,14 +711,13 @@ def TEST64rr : RI<0x85, MRMDestReg, (ops GR64:$src1, GR64:$src2),
|
||||
[(X86cmp (and GR64:$src1, GR64:$src2), 0)]>;
|
||||
def TEST64rm : RI<0x85, MRMSrcMem, (ops GR64:$src1, i64mem:$src2),
|
||||
"test{q} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)*/]>;
|
||||
[(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0)]>;
|
||||
def TEST64ri32 : RIi32<0xF7, MRM0r, (ops GR64:$src1, i64i32imm:$src2),
|
||||
"test{q} {$src2, $src1|$src1, $src2}",
|
||||
[(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0)]>;
|
||||
def TEST64mi32 : RIi32<0xF7, MRM0m, (ops i64mem:$src1, i64i32imm:$src2),
|
||||
"test{q} {$src2, $src1|$src1, $src2}",
|
||||
[/*(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2),
|
||||
0)*/]>;
|
||||
[(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0)]>;
|
||||
|
||||
def CMP64rr : RI<0x39, MRMDestReg, (ops GR64:$src1, GR64:$src2),
|
||||
"cmp{q} {$src2, $src1|$src1, $src2}",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user