diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
index ff01f355edc..3ff0779b588 100644
--- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
@@ -42,7 +42,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const
       LR->setColor(  LR->getSuggestedColor() );
       return;
     }
-    else {                              // can't allocate the suggested col
+    else if ( DEBUG_RA ) {                // can't allocate the suggested col
       cerr << " Could NOT allocate the suggested color for LR ";
       LR->printSet(); cerr << endl;
     }
@@ -192,7 +192,7 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const
       LR->setColor(  LR->getSuggestedColor() );
       return;
     }
-    else {                              // can't allocate the suggested col
+    else if (DEBUG_RA)  {                 // can't allocate the suggested col
       cerr << " Could NOT allocate the suggested color for LR ";
       LR->printSet(); cerr << endl;
     }
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 5756dc32fcb..60f4203c38c 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -621,6 +621,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(ADD, 3);
     MI->SetMachineOperand(0, SrcReg, false);
     MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
@@ -664,6 +666,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(STX, 3);
     MI->SetMachineOperand(0, DestPtrReg, false);
     MI->SetMachineOperand(1, SrcReg, false);
@@ -711,6 +715,8 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
   switch( RegType ) {
     
   case IntRegType:
+  case IntCCRegType:
+  case FloatCCRegType: 
     MI = new MachineInstr(LDX, 3);
     MI->SetMachineOperand(0, SrcPtrReg, false);
     MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,