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X86: Custom lower zext v16i8 to v16i16.

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On sandy bridge (PR17654) we now get
	vpxor	%xmm1, %xmm1, %xmm1
	vpunpckhbw	%xmm1, %xmm0, %xmm2
	vpunpcklbw	%xmm1, %xmm0, %xmm0
	vinsertf128	$1, %xmm2, %ymm0, %ymm0

On haswell it's a simple
	vpmovzxbw	%xmm0, %ymm0

There is a maze of duplicated and dead transforms and patterns in this
area. Remove the dead custom lowering of zext v8i16 to v8i32, that's
already handled by LowerAVXExtend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193262 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2013-10-23 19:19:04 +00:00
parent 531f025361
commit 7377cff9e7
4 changed files with 29 additions and 19 deletions
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25
lib/Target/X86/X86ISelLowering.cpp
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@ -1160,6 +1160,7 @@ void X86TargetLowering::resetOperationActions() {
setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
@ -8864,7 +8865,8 @@ static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
// Concat upper and lower parts.
//
if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
return SDValue();
@ -8944,24 +8946,9 @@ static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
return Res;
}
if (!VT.is256BitVector() || !SVT.is128BitVector() ||
VT.getVectorNumElements() != SVT.getVectorNumElements())
return SDValue();
assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
// AVX2 has better support of integer extending.
if (Subtarget->hasInt256())
return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
DAG.getVectorShuffle(MVT::v8i16, DL, In,
DAG.getUNDEF(MVT::v8i16),
&Mask[0]));
return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
VT.getVectorNumElements() != SVT.getVectorNumElements());
return SDValue();
}
SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {

2
lib/Target/X86/X86InstrSSE.td
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@ -5596,6 +5596,8 @@ let Predicates = [HasAVX2] in {
(VPMOVZXDQYrr VR128:$src)>;
def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
(VPMOVZXWDYrr VR128:$src)>;
def : Pat<(v16i16 (X86vzmovly (v16i8 VR128:$src))),
(VPMOVZXBWYrr VR128:$src)>;
}
def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;

12
test/CodeGen/X86/avx-zext.ll
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@ -27,3 +27,15 @@ define <8 x i32> @zext_8i8_to_8i32(<8 x i8> %z) {
%t = zext <8 x i8> %z to <8 x i32>
ret <8 x i32> %t
}
; PR17654
define <16 x i16> @zext_16i8_to_16i16(<16 x i8> %z) {
; CHECK-LABEL: zext_16i8_to_16i16:
; CHECK: vpxor
; CHECK: vpunpckhbw
; CHECK: vpunpcklbw
; CHECK: vinsertf128
; CHECK: ret
%t = zext <16 x i8> %z to <16 x i16>
ret <16 x i16> %t
}

9
test/CodeGen/X86/avx2-conversions.ll
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@ -63,6 +63,15 @@ define <8 x i32> @zext_8i8_8i32(<8 x i8> %A) nounwind {
ret <8 x i32>%B
}
; CHECK-LABEL: zext_16i8_16i16:
; CHECK: vpmovzxbw
; CHECK-NOT: vinsert
; CHECK: ret
define <16 x i16> @zext_16i8_16i16(<16 x i8> %z) {
%t = zext <16 x i8> %z to <16 x i16>
ret <16 x i16> %t
}
; CHECK: load_sext_test1
; CHECK: vpmovsxdq (%r{{[^,]*}}), %ymm{{.*}}
; CHECK: ret