mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-22 09:29:31 +00:00
Revert r199791.
It's old version which has some bugs. I'll commit lattest patch soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200179 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin
parent
ad2b41fb75
commit
73840852cf
@ -4154,70 +4154,21 @@ AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
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return false;
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}
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// Check whether a shuffle_vector could be presented as concat_vector.
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bool AArch64TargetLowering::isConcatVector(SDValue Op,SelectionDAG &DAG,
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SDValue V0, SDValue V1,
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const int* Mask,
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SDValue &Res) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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unsigned NumElts = VT.getVectorNumElements();
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unsigned V0NumElts = V0.getValueType().getVectorNumElements();
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bool isContactVector = true;
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bool splitV0 = false;
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int offset = 0;
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for (int I = 0, E = NumElts; I != E; I++){
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if (Mask[I] != I + offset) {
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if(I && !splitV0 && Mask[I] == I + (int)V0NumElts / 2) {
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splitV0 = true;
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offset = V0NumElts / 2;
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} else {
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isContactVector = false;
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break;
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}
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}
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}
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if (isContactVector) {
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EVT CastVT = EVT::getVectorVT(*DAG.getContext(),
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VT.getVectorElementType(), NumElts / 2);
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if(CastVT.getSizeInBits() < 64)
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return false;
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if (splitV0) {
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assert(V0NumElts >= NumElts / 2 &&
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"invalid operand for extract_subvector!");
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V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0,
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DAG.getConstant(0, MVT::i64));
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}
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if (NumElts != V1.getValueType().getVectorNumElements() * 2) {
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assert(V1.getValueType().getVectorNumElements() >= NumElts / 2 &&
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"invalid operand for extract_subvector!");
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V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1,
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DAG.getConstant(0, MVT::i64));
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}
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Res = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1);
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return true;
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}
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return false;
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}
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// Check whether a Build Vector could be presented as Shuffle Vector.
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// This Shuffle Vector maybe not legalized, so the length of its operand and
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// the length of result may not equal.
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// Check whether a Build Vector could be presented as Shuffle Vector. If yes,
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// try to call LowerVECTOR_SHUFFLE to lower it.
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bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
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SDValue &V0, SDValue &V1,
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int *Mask) const {
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SDValue &Res) const {
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SDLoc DL(Op);
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EVT VT = Op.getValueType();
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unsigned NumElts = VT.getVectorNumElements();
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unsigned V0NumElts = 0;
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int Mask[16];
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SDValue V0, V1;
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// Check if all elements are extracted from less than 3 vectors.
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for (unsigned i = 0; i < NumElts; ++i) {
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SDValue Elt = Op.getOperand(i);
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if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
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Elt.getOperand(0).getValueType().getVectorElementType() !=
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VT.getVectorElementType())
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if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
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return false;
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if (V0.getNode() == 0) {
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@ -4238,7 +4189,25 @@ bool AArch64TargetLowering::isKnownShuffleVector(SDValue Op, SelectionDAG &DAG,
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return false;
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}
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}
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return true;
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if (!V1.getNode() && V0NumElts == NumElts * 2) {
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V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(NumElts, MVT::i64));
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V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(0, MVT::i64));
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V0NumElts = V0.getValueType().getVectorNumElements();
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}
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if (V1.getNode() && NumElts == V0NumElts &&
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V0NumElts == V1.getValueType().getVectorNumElements()) {
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SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
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if(Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
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Res = Shuffle;
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else
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Res = LowerVECTOR_SHUFFLE(Shuffle, DAG);
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return true;
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} else
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return false;
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}
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// If this is a case we can't handle, return null and let the default
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@ -4444,31 +4413,9 @@ AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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return SDValue();
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// Try to lower this in lowering ShuffleVector way.
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SDValue V0, V1;
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int Mask[16];
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if (isKnownShuffleVector(Op, DAG, V0, V1, Mask)) {
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unsigned V0NumElts = V0.getValueType().getVectorNumElements();
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if (!V1.getNode() && V0NumElts == NumElts * 2) {
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V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(NumElts, MVT::i64));
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V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V0,
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DAG.getConstant(0, MVT::i64));
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V0NumElts = V0.getValueType().getVectorNumElements();
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}
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if (V1.getNode() && NumElts == V0NumElts &&
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V0NumElts == V1.getValueType().getVectorNumElements()) {
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SDValue Shuffle = DAG.getVectorShuffle(VT, DL, V0, V1, Mask);
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if(Shuffle.getOpcode() != ISD::VECTOR_SHUFFLE)
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return Shuffle;
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else
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return LowerVECTOR_SHUFFLE(Shuffle, DAG);
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} else {
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SDValue Res;
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if(isConcatVector(Op, DAG, V0, V1, Mask, Res))
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return Res;
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}
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}
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SDValue Shuf;
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if (isKnownShuffleVector(Op, DAG, Shuf))
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return Shuf;
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// If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
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// know the default expansion would otherwise fall back on something even
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@ -4654,10 +4601,6 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
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return DAG.getNode(ISDNo, dl, VT, V1, V2);
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}
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SDValue Res;
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if (isConcatVector(Op, DAG, V1, V2, &ShuffleMask[0], Res))
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return Res;
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// If the element of shuffle mask are all the same constant, we can
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// transform it into either NEON_VDUP or NEON_VDUPLANE
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if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
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@ -232,11 +232,7 @@ public:
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SDLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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bool isConcatVector(SDValue Op,SelectionDAG &DAG, SDValue V0, SDValue V1,
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const int* Mask, SDValue &Res) const;
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bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &V0,
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SDValue &V1, int *Mask) const;
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bool isKnownShuffleVector(SDValue Op, SelectionDAG &DAG, SDValue &Res) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
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const AArch64Subtarget *ST) const;
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@ -975,14 +975,6 @@ entry:
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declare float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float>)
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define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
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; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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ret <16 x i8> %vecinit30
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}
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define <2 x i32> @test_concat_undef_v1i32(<1 x i32> %a) {
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; CHECK-LABEL: test_concat_undef_v1i32:
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; CHECK: ins v{{[0-9]+}}.s[1], v{{[0-9]+}}.s[0]
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@ -1029,268 +1021,6 @@ entry:
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ret <2 x i32> %h
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}
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define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
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; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecext = extractelement <8 x i8> %x, i32 0
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%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
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%vecext1 = extractelement <8 x i8> %x, i32 1
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%vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
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%vecext3 = extractelement <8 x i8> %x, i32 2
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%vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
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%vecext5 = extractelement <8 x i8> %x, i32 3
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%vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
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%vecext7 = extractelement <8 x i8> %x, i32 4
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%vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
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%vecext9 = extractelement <8 x i8> %x, i32 5
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%vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
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%vecext11 = extractelement <8 x i8> %x, i32 6
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%vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
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%vecext13 = extractelement <8 x i8> %x, i32 7
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%vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
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%vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
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ret <16 x i8> %vecinit30
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}
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define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
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; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecext = extractelement <16 x i8> %x, i32 0
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%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
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%vecext1 = extractelement <16 x i8> %x, i32 1
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%vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
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%vecext3 = extractelement <16 x i8> %x, i32 2
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%vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
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%vecext5 = extractelement <16 x i8> %x, i32 3
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%vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
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%vecext7 = extractelement <16 x i8> %x, i32 4
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%vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
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%vecext9 = extractelement <16 x i8> %x, i32 5
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%vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
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%vecext11 = extractelement <16 x i8> %x, i32 6
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%vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
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%vecext13 = extractelement <16 x i8> %x, i32 7
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%vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
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%vecext15 = extractelement <8 x i8> %y, i32 0
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%vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 8
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%vecext17 = extractelement <8 x i8> %y, i32 1
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%vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 9
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%vecext19 = extractelement <8 x i8> %y, i32 2
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%vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 10
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%vecext21 = extractelement <8 x i8> %y, i32 3
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%vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 11
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%vecext23 = extractelement <8 x i8> %y, i32 4
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%vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 12
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%vecext25 = extractelement <8 x i8> %y, i32 5
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%vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 13
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%vecext27 = extractelement <8 x i8> %y, i32 6
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%vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
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%vecext29 = extractelement <8 x i8> %y, i32 7
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%vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
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ret <16 x i8> %vecinit30
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}
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define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
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; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecext = extractelement <8 x i8> %x, i32 0
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%vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
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%vecext1 = extractelement <8 x i8> %x, i32 1
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%vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
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%vecext3 = extractelement <8 x i8> %x, i32 2
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%vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
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%vecext5 = extractelement <8 x i8> %x, i32 3
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%vecinit6 = insertelement <16 x i8> %vecinit4, i8 %vecext5, i32 3
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%vecext7 = extractelement <8 x i8> %x, i32 4
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%vecinit8 = insertelement <16 x i8> %vecinit6, i8 %vecext7, i32 4
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%vecext9 = extractelement <8 x i8> %x, i32 5
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%vecinit10 = insertelement <16 x i8> %vecinit8, i8 %vecext9, i32 5
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%vecext11 = extractelement <8 x i8> %x, i32 6
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%vecinit12 = insertelement <16 x i8> %vecinit10, i8 %vecext11, i32 6
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%vecext13 = extractelement <8 x i8> %x, i32 7
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%vecinit14 = insertelement <16 x i8> %vecinit12, i8 %vecext13, i32 7
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%vecext15 = extractelement <8 x i8> %y, i32 0
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%vecinit16 = insertelement <16 x i8> %vecinit14, i8 %vecext15, i32 8
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%vecext17 = extractelement <8 x i8> %y, i32 1
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%vecinit18 = insertelement <16 x i8> %vecinit16, i8 %vecext17, i32 9
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%vecext19 = extractelement <8 x i8> %y, i32 2
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%vecinit20 = insertelement <16 x i8> %vecinit18, i8 %vecext19, i32 10
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%vecext21 = extractelement <8 x i8> %y, i32 3
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%vecinit22 = insertelement <16 x i8> %vecinit20, i8 %vecext21, i32 11
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%vecext23 = extractelement <8 x i8> %y, i32 4
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%vecinit24 = insertelement <16 x i8> %vecinit22, i8 %vecext23, i32 12
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%vecext25 = extractelement <8 x i8> %y, i32 5
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%vecinit26 = insertelement <16 x i8> %vecinit24, i8 %vecext25, i32 13
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%vecext27 = extractelement <8 x i8> %y, i32 6
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%vecinit28 = insertelement <16 x i8> %vecinit26, i8 %vecext27, i32 14
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%vecext29 = extractelement <8 x i8> %y, i32 7
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%vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
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ret <16 x i8> %vecinit30
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}
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define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
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; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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ret <8 x i16> %vecinit14
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}
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define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
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; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
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; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
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entry:
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%vecext = extractelement <4 x i16> %x, i32 0
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%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
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%vecext1 = extractelement <4 x i16> %x, i32 1
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%vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
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%vecext3 = extractelement <4 x i16> %x, i32 2
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%vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
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%vecext5 = extractelement <4 x i16> %x, i32 3
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%vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
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%vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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ret <8 x i16> %vecinit14
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}
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define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <8 x i16> %x, i32 0
|
||||
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
|
||||
%vecext1 = extractelement <8 x i16> %x, i32 1
|
||||
%vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
|
||||
%vecext3 = extractelement <8 x i16> %x, i32 2
|
||||
%vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
|
||||
%vecext5 = extractelement <8 x i16> %x, i32 3
|
||||
%vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
|
||||
%vecext7 = extractelement <4 x i16> %y, i32 0
|
||||
%vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
|
||||
%vecext9 = extractelement <4 x i16> %y, i32 1
|
||||
%vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
|
||||
%vecext11 = extractelement <4 x i16> %y, i32 2
|
||||
%vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
|
||||
%vecext13 = extractelement <4 x i16> %y, i32 3
|
||||
%vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
|
||||
ret <8 x i16> %vecinit14
|
||||
}
|
||||
|
||||
define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <4 x i16> %x, i32 0
|
||||
%vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
|
||||
%vecext1 = extractelement <4 x i16> %x, i32 1
|
||||
%vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
|
||||
%vecext3 = extractelement <4 x i16> %x, i32 2
|
||||
%vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
|
||||
%vecext5 = extractelement <4 x i16> %x, i32 3
|
||||
%vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
|
||||
%vecext7 = extractelement <4 x i16> %y, i32 0
|
||||
%vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
|
||||
%vecext9 = extractelement <4 x i16> %y, i32 1
|
||||
%vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
|
||||
%vecext11 = extractelement <4 x i16> %y, i32 2
|
||||
%vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
|
||||
%vecext13 = extractelement <4 x i16> %y, i32 3
|
||||
%vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
|
||||
ret <8 x i16> %vecinit14
|
||||
}
|
||||
|
||||
define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
ret <4 x i32> %vecinit6
|
||||
}
|
||||
|
||||
define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <2 x i32> %x, i32 0
|
||||
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
||||
%vecext1 = extractelement <2 x i32> %x, i32 1
|
||||
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
||||
%vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
||||
ret <4 x i32> %vecinit6
|
||||
}
|
||||
|
||||
define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <4 x i32> %x, i32 0
|
||||
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
||||
%vecext1 = extractelement <4 x i32> %x, i32 1
|
||||
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
||||
%vecext3 = extractelement <2 x i32> %y, i32 0
|
||||
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
|
||||
%vecext5 = extractelement <2 x i32> %y, i32 1
|
||||
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
|
||||
ret <4 x i32> %vecinit6
|
||||
}
|
||||
|
||||
define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <2 x i32> %x, i32 0
|
||||
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
||||
%vecext1 = extractelement <2 x i32> %x, i32 1
|
||||
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
||||
%vecext3 = extractelement <2 x i32> %y, i32 0
|
||||
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
|
||||
%vecext5 = extractelement <2 x i32> %y, i32 1
|
||||
%vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
|
||||
ret <4 x i32> %vecinit6
|
||||
}
|
||||
|
||||
define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecinit2 = shufflevector <2 x i64> %x, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
|
||||
ret <2 x i64> %vecinit2
|
||||
}
|
||||
|
||||
define <2 x i64> @test_concat_v2i64_v1i64_v2i64(<1 x i64> %x, <2 x i64> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v2i64_v1i64_v2i64:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <1 x i64> %x, i32 0
|
||||
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
|
||||
%vecinit2 = shufflevector <2 x i64> %vecinit, <2 x i64> %y, <2 x i32> <i32 0, i32 2>
|
||||
ret <2 x i64> %vecinit2
|
||||
}
|
||||
|
||||
define <2 x i64> @test_concat_v2i64_v2i64_v1i64(<2 x i64> %x, <1 x i64> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v2i64_v2i64_v1i64:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <2 x i64> %x, i32 0
|
||||
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
|
||||
%vecext1 = extractelement <1 x i64> %y, i32 0
|
||||
%vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
|
||||
ret <2 x i64> %vecinit2
|
||||
}
|
||||
|
||||
define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
|
||||
; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
|
||||
; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0]
|
||||
entry:
|
||||
%vecext = extractelement <1 x i64> %x, i32 0
|
||||
%vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
|
||||
%vecext1 = extractelement <1 x i64> %y, i32 0
|
||||
%vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
|
||||
ret <2 x i64> %vecinit2
|
||||
}
|
||||
|
||||
declare <1 x i16> @llvm.aarch64.neon.vsqadd.v1i16(<1 x i16>, <1 x i16>)
|
||||
|
||||
define <1 x i16> @test_copy_FPR16_FPR16(<1 x i16> %a, <1 x i16> %b) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user