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NEON VLD/VST are now fully implemented. For operations that expand to

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multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84036 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-13 21:55:24 +00:00
parent 1bf5ebc7be
commit 73d64a6fd3
1 changed files with 2 additions and 48 deletions
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50
lib/Target/ARM/ARMISelLowering.cpp
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@ -1369,44 +1369,11 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
} }
static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) {
SDNode *Node = Op.getNode();
EVT VT = Node->getValueType(0);
// No expansion needed for 64-bit vectors.
if (VT.is64BitVector())
return SDValue();
// FIXME: We need to expand VLD3 and VLD4 of 128-bit vectors into separate
// operations to load the even and odd registers.
return SDValue();
}
static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) {
SDNode *Node = Op.getNode();
EVT VT = Node->getOperand(3).getValueType();
// No expansion needed for 64-bit vectors.
if (VT.is64BitVector())
return SDValue();
// FIXME: We need to expand VST3 and VST4 of 128-bit vectors into separate
// operations to store the even and odd registers.
return SDValue();
}
static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG, static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) { unsigned NumVecs) {
SDNode *Node = Op.getNode();
EVT VT = Node->getValueType(0);
if (!VT.is64BitVector())
return SDValue(); // unimplemented
// Change the lane number operand to be a TargetConstant; otherwise it // Change the lane number operand to be a TargetConstant; otherwise it
// will be legalized into a register. // will be legalized into a register.
SDNode *Node = Op.getNode();
ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3)); ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
if (!Lane) { if (!Lane) {
assert(false && "vld lane number must be a constant"); assert(false && "vld lane number must be a constant");
@ -1419,14 +1386,9 @@ static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG, static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
unsigned NumVecs) { unsigned NumVecs) {
SDNode *Node = Op.getNode();
EVT VT = Node->getOperand(3).getValueType();
if (!VT.is64BitVector())
return SDValue(); // unimplemented
// Change the lane number operand to be a TargetConstant; otherwise it // Change the lane number operand to be a TargetConstant; otherwise it
// will be legalized into a register. // will be legalized into a register.
SDNode *Node = Op.getNode();
ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3)); ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
if (!Lane) { if (!Lane) {
assert(false && "vst lane number must be a constant"); assert(false && "vst lane number must be a constant");
@ -1441,20 +1403,12 @@ SDValue
ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) { ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
switch (IntNo) { switch (IntNo) {
case Intrinsic::arm_neon_vld3:
return LowerNeonVLDIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vld4:
return LowerNeonVLDIntrinsic(Op, DAG, 4);
case Intrinsic::arm_neon_vld2lane: case Intrinsic::arm_neon_vld2lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 2); return LowerNeonVLDLaneIntrinsic(Op, DAG, 2);
case Intrinsic::arm_neon_vld3lane: case Intrinsic::arm_neon_vld3lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 3); return LowerNeonVLDLaneIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vld4lane: case Intrinsic::arm_neon_vld4lane:
return LowerNeonVLDLaneIntrinsic(Op, DAG, 4); return LowerNeonVLDLaneIntrinsic(Op, DAG, 4);
case Intrinsic::arm_neon_vst3:
return LowerNeonVSTIntrinsic(Op, DAG, 3);
case Intrinsic::arm_neon_vst4:
return LowerNeonVSTIntrinsic(Op, DAG, 4);
case Intrinsic::arm_neon_vst2lane: case Intrinsic::arm_neon_vst2lane:
return LowerNeonVSTLaneIntrinsic(Op, DAG, 2); return LowerNeonVSTLaneIntrinsic(Op, DAG, 2);
case Intrinsic::arm_neon_vst3lane: case Intrinsic::arm_neon_vst3lane: