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Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc

Browse Source 
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2011-06-27 18:32:37 +00:00
parent 4ef4c171db
commit 73f50d9bc3
71 changed files with 295 additions and 256 deletions
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utils/TableGen/TableGen.cpp
+2 -17
View File
@@ -54,7 +54,7 @@ using namespace llvm;
enum ActionType {
PrintRecords,
GenEmitter,
GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
GenRegisterInfo,
GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
GenARMDecoder,
GenDisassembler,
@@ -93,14 +93,8 @@ namespace {
"Print all records to stdout (default)"),
clEnumValN(GenEmitter, "gen-emitter",
"Generate machine code emitter"),
clEnumValN(GenRegisterEnums, "gen-register-enums",
"Generate enum values for registers"),
clEnumValN(GenRegisterDesc, "gen-register-desc",
"Generate register descriptions"),
clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers & reg-classes info"),
clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
"Generate registers & reg-classes info header"),
"Generate registers and register classes info"),
clEnumValN(GenInstrEnums, "gen-instr-enums",
"Generate enum values for instructions"),
clEnumValN(GenInstrs, "gen-instr-desc",
@@ -263,18 +257,9 @@ int main(int argc, char **argv) {
case GenEmitter:
CodeEmitterGen(Records).run(Out.os());
break;
case GenRegisterEnums:
RegisterInfoEmitter(Records).runEnums(Out.os());
break;
case GenRegisterDesc:
RegisterInfoEmitter(Records).runDesc(Out.os());
break;
case GenRegisterInfo:
RegisterInfoEmitter(Records).run(Out.os());
break;
case GenRegisterInfoHeader:
RegisterInfoEmitter(Records).runHeader(Out.os());
break;
case GenInstrEnums:
InstrEnumEmitter(Records).run(Out.os());
break;