From 7417d92e56889d4d0cba47e076941db77e99f355 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Fri, 30 Jan 2015 01:40:59 +0000 Subject: [PATCH] Migrate NVPTXISelDAGToDAG's getSubtarget to a runOnMachineFunction version. Update NVPTXInstrInfo accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227538 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 66 ++++++++++++++------------ lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 4 +- lib/Target/NVPTX/NVPTXInstrInfo.td | 38 +++++++-------- 3 files changed, 56 insertions(+), 52 deletions(-) diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp index cd0422d78a8..9244693c347 100644 --- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp +++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp @@ -50,11 +50,15 @@ FunctionPass *llvm::createNVPTXISelDag(NVPTXTargetMachine &TM, NVPTXDAGToDAGISel::NVPTXDAGToDAGISel(NVPTXTargetMachine &tm, CodeGenOpt::Level OptLevel) - : SelectionDAGISel(tm, OptLevel), - Subtarget(tm.getSubtarget()) { + : SelectionDAGISel(tm, OptLevel) { doMulWide = (OptLevel > 0); } +bool NVPTXDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &static_cast(MF.getSubtarget()); + return SelectionDAGISel::runOnMachineFunction(MF); +} + int NVPTXDAGToDAGISel::getDivF32Level() const { if (UsePrecDivF32.getNumOccurrences() > 0) { // If nvptx-prec-div32=N is used on the command-line, always honor it @@ -98,7 +102,7 @@ bool NVPTXDAGToDAGISel::useF32FTZ() const { } bool NVPTXDAGToDAGISel::allowFMA() const { - const NVPTXTargetLowering *TL = Subtarget.getTargetLowering(); + const NVPTXTargetLowering *TL = Subtarget->getTargetLowering(); return TL->allowFMA(*MF, OptLevel); } @@ -526,7 +530,7 @@ SDNode *NVPTXDAGToDAGISel::SelectIntrinsicChain(SDNode *N) { } static unsigned int getCodeAddrSpace(MemSDNode *N, - const NVPTXSubtarget &Subtarget) { + const NVPTXSubtarget *Subtarget) { const Value *Src = N->getMemOperand()->getValue(); if (!Src) @@ -579,19 +583,19 @@ SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) { switch (SrcAddrSpace) { default: report_fatal_error("Bad address space in addrspacecast"); case ADDRESS_SPACE_GLOBAL: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_global_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; break; case ADDRESS_SPACE_SHARED: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_shared_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes; break; case ADDRESS_SPACE_CONST: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_const_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes; break; case ADDRESS_SPACE_LOCAL: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_local_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes; break; } @@ -604,19 +608,19 @@ SDNode *NVPTXDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) { switch (DstAddrSpace) { default: report_fatal_error("Bad address space in addrspacecast"); case ADDRESS_SPACE_GLOBAL: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_global_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_global_yes_64 : NVPTX::cvta_to_global_yes; break; case ADDRESS_SPACE_SHARED: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_shared_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_shared_yes_64 : NVPTX::cvta_to_shared_yes; break; case ADDRESS_SPACE_CONST: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_const_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_const_yes_64 : NVPTX::cvta_to_const_yes; break; case ADDRESS_SPACE_LOCAL: - Opc = Subtarget.is64Bit() ? NVPTX::cvta_to_local_yes_64 + Opc = Subtarget->is64Bit() ? NVPTX::cvta_to_local_yes_64 : NVPTX::cvta_to_local_yes; break; } @@ -713,7 +717,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) { getI32Imm(vecType), getI32Imm(fromType), getI32Imm(fromTypeWidth), Addr, Chain }; NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRsi64(N1.getNode(), N1, Base, Offset) : SelectADDRsi(N1.getNode(), N1, Base, Offset)) { switch (TargetVT) { @@ -742,10 +746,10 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) { getI32Imm(vecType), getI32Imm(fromType), getI32Imm(fromTypeWidth), Base, Offset, Chain }; NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRri64(N1.getNode(), N1, Base, Offset) : SelectADDRri(N1.getNode(), N1, Base, Offset)) { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (TargetVT) { case MVT::i8: Opcode = NVPTX::LD_i8_ari_64; @@ -797,7 +801,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoad(SDNode *N) { getI32Imm(fromTypeWidth), Base, Offset, Chain }; NVPTXLD = CurDAG->getMachineNode(Opcode, dl, TargetVT, MVT::Other, Ops); } else { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (TargetVT) { case MVT::i8: Opcode = NVPTX::LD_i8_areg_64; @@ -974,7 +978,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) { getI32Imm(VecType), getI32Imm(FromType), getI32Imm(FromTypeWidth), Addr, Chain }; LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRsi64(Op1.getNode(), Op1, Base, Offset) : SelectADDRsi(Op1.getNode(), Op1, Base, Offset)) { switch (N->getOpcode()) { @@ -1028,10 +1032,10 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) { getI32Imm(VecType), getI32Imm(FromType), getI32Imm(FromTypeWidth), Base, Offset, Chain }; LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset) : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; @@ -1133,7 +1137,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLoadVector(SDNode *N) { LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); } else { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; @@ -1425,10 +1429,10 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) { SDValue Ops[] = { Addr, Chain }; LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRri64(Op1.getNode(), Op1, Base, Offset) : SelectADDRri(Op1.getNode(), Op1, Base, Offset)) { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; @@ -1710,7 +1714,7 @@ SDNode *NVPTXDAGToDAGISel::SelectLDGLDU(SDNode *N) { LD = CurDAG->getMachineNode(Opcode, DL, N->getVTList(), Ops); } else { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; @@ -2083,7 +2087,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) { getI32Imm(vecType), getI32Imm(toType), getI32Imm(toTypeWidth), Addr, Chain }; NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset) : SelectADDRsi(N2.getNode(), N2, Base, Offset)) { switch (SourceVT) { @@ -2112,10 +2116,10 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) { getI32Imm(vecType), getI32Imm(toType), getI32Imm(toTypeWidth), Base, Offset, Chain }; NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset) : SelectADDRri(N2.getNode(), N2, Base, Offset)) { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (SourceVT) { case MVT::i8: Opcode = NVPTX::ST_i8_ari_64; @@ -2167,7 +2171,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStore(SDNode *N) { getI32Imm(toTypeWidth), Base, Offset, Chain }; NVPTXST = CurDAG->getMachineNode(Opcode, dl, MVT::Other, Ops); } else { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (SourceVT) { case MVT::i8: Opcode = NVPTX::ST_i8_areg_64; @@ -2344,7 +2348,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) { break; } StOps.push_back(Addr); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset) : SelectADDRsi(N2.getNode(), N2, Base, Offset)) { switch (N->getOpcode()) { @@ -2395,10 +2399,10 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) { } StOps.push_back(Base); StOps.push_back(Offset); - } else if (Subtarget.is64Bit() + } else if (Subtarget->is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset) : SelectADDRri(N2.getNode(), N2, Base, Offset)) { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; @@ -2496,7 +2500,7 @@ SDNode *NVPTXDAGToDAGISel::SelectStoreVector(SDNode *N) { StOps.push_back(Base); StOps.push_back(Offset); } else { - if (Subtarget.is64Bit()) { + if (Subtarget->is64Bit()) { switch (N->getOpcode()) { default: return nullptr; diff --git a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h index 69afcd7320d..1548c920c0e 100644 --- a/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ b/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -43,8 +43,8 @@ public: const char *getPassName() const override { return "NVPTX DAG->DAG Pattern Instruction Selection"; } - - const NVPTXSubtarget &Subtarget; + bool runOnMachineFunction(MachineFunction &MF) override; + const NVPTXSubtarget *Subtarget; bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.td b/lib/Target/NVPTX/NVPTXInstrInfo.td index 1c63668f0dd..68f0d9fa41e 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.td +++ b/lib/Target/NVPTX/NVPTXInstrInfo.td @@ -117,24 +117,24 @@ def F32ConstOne : Operand, PatLeaf<(f32 fpimm)>, SDNodeXForm; -def hasAtomRedS32 : Predicate<"Subtarget.hasAtomRedS32()">; -def hasAtomRedGen32 : Predicate<"Subtarget.hasAtomRedGen32()">; +def hasAtomRedG32 : Predicate<"Subtarget->hasAtomRedG32()">; +def hasAtomRedS32 : Predicate<"Subtarget->hasAtomRedS32()">; +def hasAtomRedGen32 : Predicate<"Subtarget->hasAtomRedGen32()">; def useAtomRedG32forGen32 : - Predicate<"!Subtarget.hasAtomRedGen32() && Subtarget.hasAtomRedG32()">; -def hasBrkPt : Predicate<"Subtarget.hasBrkPt()">; -def hasAtomRedG64 : Predicate<"Subtarget.hasAtomRedG64()">; -def hasAtomRedS64 : Predicate<"Subtarget.hasAtomRedS64()">; -def hasAtomRedGen64 : Predicate<"Subtarget.hasAtomRedGen64()">; + Predicate<"!Subtarget->hasAtomRedGen32() && Subtarget->hasAtomRedG32()">; +def hasBrkPt : Predicate<"Subtarget->hasBrkPt()">; +def hasAtomRedG64 : Predicate<"Subtarget->hasAtomRedG64()">; +def hasAtomRedS64 : Predicate<"Subtarget->hasAtomRedS64()">; +def hasAtomRedGen64 : Predicate<"Subtarget->hasAtomRedGen64()">; def useAtomRedG64forGen64 : - Predicate<"!Subtarget.hasAtomRedGen64() && Subtarget.hasAtomRedG64()">; -def hasAtomAddF32 : Predicate<"Subtarget.hasAtomAddF32()">; -def hasVote : Predicate<"Subtarget.hasVote()">; -def hasDouble : Predicate<"Subtarget.hasDouble()">; -def reqPTX20 : Predicate<"Subtarget.reqPTX20()">; -def hasLDG : Predicate<"Subtarget.hasLDG()">; -def hasLDU : Predicate<"Subtarget.hasLDU()">; -def hasGenericLdSt : Predicate<"Subtarget.hasGenericLdSt()">; + Predicate<"!Subtarget->hasAtomRedGen64() && Subtarget->hasAtomRedG64()">; +def hasAtomAddF32 : Predicate<"Subtarget->hasAtomAddF32()">; +def hasVote : Predicate<"Subtarget->hasVote()">; +def hasDouble : Predicate<"Subtarget->hasDouble()">; +def reqPTX20 : Predicate<"Subtarget->reqPTX20()">; +def hasLDG : Predicate<"Subtarget->hasLDG()">; +def hasLDU : Predicate<"Subtarget->hasLDU()">; +def hasGenericLdSt : Predicate<"Subtarget->hasGenericLdSt()">; def doF32FTZ : Predicate<"useF32FTZ()">; def doNoF32FTZ : Predicate<"!useF32FTZ()">; @@ -150,12 +150,12 @@ def do_DIVF32_FULL : Predicate<"getDivF32Level()==1">; def do_SQRTF32_APPROX : Predicate<"!usePrecSqrtF32()">; def do_SQRTF32_RN : Predicate<"usePrecSqrtF32()">; -def hasHWROT32 : Predicate<"Subtarget.hasHWROT32()">; -def noHWROT32 : Predicate<"!Subtarget.hasHWROT32()">; +def hasHWROT32 : Predicate<"Subtarget->hasHWROT32()">; +def noHWROT32 : Predicate<"!Subtarget->hasHWROT32()">; def true : Predicate<"1">; -def hasPTX31 : Predicate<"Subtarget.getPTXVersion() >= 31">; +def hasPTX31 : Predicate<"Subtarget->getPTXVersion() >= 31">; //===----------------------------------------------------------------------===//