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[mips] Add support for .cpsetup
Summary: Patch by Robert N. M. Watson His work was sponsored by: DARPA, AFRL Small corrections by myself. CC: theraven, matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3199 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204924 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -196,6 +196,7 @@ class MipsAsmParser : public MCTargetAsmParser {
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bool isEvaluated(const MCExpr *Expr);
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bool parseSetFeature(uint64_t Feature);
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bool parseDirectiveCPSetup();
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bool parseDirectiveSet();
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bool parseDirectiveOption();
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@ -229,6 +230,10 @@ class MipsAsmParser : public MCTargetAsmParser {
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return STI.getFeatureBits() & Mips::FeatureMicroMips;
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}
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bool parseRegister(unsigned &RegNum);
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bool eatComma(StringRef ErrorStr);
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int matchRegisterName(StringRef Symbol, bool is64BitReg);
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int matchCPURegisterName(StringRef Symbol);
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@ -249,6 +254,8 @@ class MipsAsmParser : public MCTargetAsmParser {
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unsigned getReg(int RC, int RegNo);
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unsigned getGPR(int RegNo);
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int getATReg();
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// Warn if RegNo is the current assembler temporary.
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@ -1202,6 +1209,12 @@ unsigned MipsAsmParser::getReg(int RC, int RegNo) {
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return *(getContext().getRegisterInfo()->getRegClass(RC).begin() + RegNo);
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}
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unsigned MipsAsmParser::getGPR(int RegNo) {
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return getReg((isMips64()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID,
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RegNo);
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}
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int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) {
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if (RegNum >
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getContext().getRegisterInfo()->getRegClass(RegClass).getNumRegs())
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@ -2501,6 +2514,123 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
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return false;
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}
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bool MipsAsmParser::parseRegister(unsigned &RegNum) {
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if (!getLexer().is(AsmToken::Dollar))
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return false;
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Parser.Lex();
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const AsmToken &Reg = Parser.getTok();
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if (Reg.is(AsmToken::Identifier)) {
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RegNum = matchCPURegisterName(Reg.getIdentifier());
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} else if (Reg.is(AsmToken::Integer)) {
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RegNum = Reg.getIntVal();
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} else {
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return false;
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}
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Parser.Lex();
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return true;
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}
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bool MipsAsmParser::eatComma(StringRef ErrorStr) {
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if (getLexer().isNot(AsmToken::Comma)) {
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SMLoc Loc = getLexer().getLoc();
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Parser.eatToEndOfStatement();
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return Error(Loc, ErrorStr);
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}
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Parser.Lex(); // Eat the comma.
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return true;
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}
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bool MipsAsmParser::parseDirectiveCPSetup() {
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unsigned FuncReg;
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unsigned Save;
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bool SaveIsReg = true;
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if (!parseRegister(FuncReg))
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return reportParseError("expected register containing function address");
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FuncReg = getGPR(FuncReg);
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if (!eatComma("expected comma parsing directive"))
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return true;
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if (!parseRegister(Save)) {
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const AsmToken &Tok = Parser.getTok();
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if (Tok.is(AsmToken::Integer)) {
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Save = Tok.getIntVal();
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SaveIsReg = false;
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Parser.Lex();
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} else
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return reportParseError("expected save register or stack offset");
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} else
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Save = getGPR(Save);
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if (!eatComma("expected comma parsing directive"))
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return true;
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StringRef Name;
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if (Parser.parseIdentifier(Name))
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reportParseError("expected identifier");
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MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
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unsigned GPReg = getGPR(matchCPURegisterName("gp"));
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// FIXME: The code below this point should be in the TargetStreamers.
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// Only N32 and N64 emit anything for .cpsetup
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// FIXME: We should only emit something for PIC mode too.
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if (!isN32() && !isN64())
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return false;
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MCStreamer &TS = getStreamer();
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MCInst Inst;
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// Either store the old $gp in a register or on the stack
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if (SaveIsReg) {
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// move $save, $gpreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(Save));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(getGPR(0)));
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} else {
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// sd $gpreg, offset($sp)
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Inst.setOpcode(Mips::SD);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(getGPR(matchCPURegisterName("sp"))));
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Inst.addOperand(MCOperand::CreateImm(Save));
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}
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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const MCSymbolRefExpr *HiExpr = MCSymbolRefExpr::Create(
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Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_HI,
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getContext());
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const MCSymbolRefExpr *LoExpr = MCSymbolRefExpr::Create(
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Sym->getName(), MCSymbolRefExpr::VK_Mips_GPOFF_LO,
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getContext());
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// lui $gp, %hi(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::LUi);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateExpr(HiExpr));
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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// addiu $gp, $gp, %lo(%neg(%gp_rel(funcSym)))
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Inst.setOpcode(Mips::ADDiu);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateExpr(LoExpr));
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TS.EmitInstruction(Inst, STI);
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Inst.clear();
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// daddu $gp, $gp, $funcreg
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Inst.setOpcode(Mips::DADDu);
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(GPReg));
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Inst.addOperand(MCOperand::CreateReg(FuncReg));
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TS.EmitInstruction(Inst, STI);
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return false;
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}
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bool MipsAsmParser::parseDirectiveSet() {
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// Get the next token.
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@ -2692,6 +2822,9 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) {
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return false;
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}
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if (IDVal == ".cpsetup")
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return parseDirectiveCPSetup();
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return true;
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}
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36
test/MC/Mips/cpsetup.s
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36
test/MC/Mips/cpsetup.s
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@ -0,0 +1,36 @@
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=O32 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N32 %s
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# RUN: llvm-mc -triple mips64-unknown-unknown %s | \
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# RUN: FileCheck -check-prefix=ANY -check-prefix=NXX -check-prefix=N64 %s
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# TODO: !PIC -> no output
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.text
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.option pic2
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t1:
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.cpsetup $25, 8, __cerror
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# ANY-LABEL: t1:
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# O32-NOT: __cerror
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# NXX: sd $gp, 8($sp)
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# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror)))
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# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror)))
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# N32: addu $gp, $gp, $25
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# N64: daddu $gp, $gp, $25
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t2:
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# ANY-LABEL: t2:
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.cpsetup $25, $2, __cerror
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# O32-NOT: __cerror
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# NXX: move $2, $gp
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# NXX: lui $gp, %hi(%neg(%gp_rel(__cerror)))
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# NXX: addiu $gp, $gp, %lo(%neg(%gp_rel(__cerror)))
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# N32: addu $gp, $gp, $25
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# N64: daddu $gp, $gp, $25
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