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[fast-isel] Add support for SUBs with non-legal types.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150047 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-02-08 02:45:44 +00:00
parent 176346d021
commit 743e19983e
2 changed files with 43 additions and 0 deletions
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5
lib/Target/ARM/ARMFastISel.cpp
View File

@ -1749,6 +1749,9 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
case ISD::OR:
Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
break;
case ISD::SUB:
Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
break;
}
unsigned SrcReg1 = getRegForValue(I->getOperand(0));
@ -2509,6 +2512,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
return SelectBinaryIntOp(I, ISD::ADD);
case Instruction::Or:
return SelectBinaryIntOp(I, ISD::OR);
case Instruction::Sub:
return SelectBinaryIntOp(I, ISD::SUB);
case Instruction::FAdd:
return SelectBinaryFPOp(I, ISD::FADD);
case Instruction::FSub:

38
test/CodeGen/ARM/fast-isel-binary.ll
View File

@ -76,3 +76,41 @@ entry:
store i16 %0, i16* %a.addr, align 4
ret void
}
; Test sub with non-legal types
define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
entry:
; ARM: sub_i1
; THUMB: sub_i1
%a.addr = alloca i1, align 4
%0 = sub i1 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
store i1 %0, i1* %a.addr, align 4
ret void
}
define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
entry:
; ARM: sub_i8
; THUMB: sub_i8
%a.addr = alloca i8, align 4
%0 = sub i8 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
entry:
; ARM: sub_i16
; THUMB: sub_i16
%a.addr = alloca i16, align 4
%0 = sub i16 %a, %b
; ARM: sub r0, r0, r1
; THUMB: subs r0, r0, r1
store i16 %0, i16* %a.addr, align 4
ret void
}