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ARM assemly parsing and validation of IT instruction.

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"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."

PR11853

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2012-01-25 19:52:01 +00:00
parent 0c8515f096
commit 74423e32ce
3 changed files with 25 additions and 3 deletions
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4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -5179,3 +5179,7 @@ def : ARMInstAlias<"mul${s}${p} $Rn, $Rm",
// "neg" is and alias for "rsb rd, rn, #0"
def : ARMInstAlias<"neg${s}${p} $Rd, $Rm",
(RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>;
// 'it' blocks in ARM mode just validate the predicates. The IT itself
// is discarded.
def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>;

13
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -5080,10 +5080,11 @@ validateInstruction(MCInst &Inst,
const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
SMLoc Loc = Operands[0]->getStartLoc();
// Check the IT block state first.
// NOTE: In Thumb mode, the BKPT instruction has the interesting property of
// being allowed in IT blocks, but not being predicable. It just always
// NOTE: BKPT instruction has the interesting property of being
// allowed in IT blocks, but not being predicable. It just always
// executes.
if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
Inst.getOpcode() != ARM::BKPT) {
unsigned bit = 1;
if (ITState.FirstCond)
ITState.FirstCond = false;
@ -7048,6 +7049,7 @@ processInstruction(MCInst &Inst,
}
return false;
}
case ARM::ITasm:
case ARM::t2IT: {
// The mask bits for all but the first condition are represented as
// the low bit of the condition code value implies 't'. We currently
@ -7154,6 +7156,11 @@ MatchAndEmitInstruction(SMLoc IDLoc,
// block.
forwardITPosition();
// ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
// doesn't actually encode.
if (Inst.getOpcode() == ARM::ITasm)
return false;
Out.EmitInstruction(Inst);
return false;
case Match_MissingFeature:

11
test/MC/ARM/arm-it-block.s Normal file
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@ -0,0 +1,11 @@
@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
.syntax unified
.globl _func
_func:
@ CHECK: _func:
it eq
moveq r2, r3
@ 'it' is parsed but not encoded.
@ CHECK-NOT: it
@ CHECK: moveq r2, r3 @ encoding: [0x03,0x20,0xa0,0x01]