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SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue

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shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-05-29 17:03:36 +00:00
parent 0f9c658558
commit 7451d3e09d
6 changed files with 50 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
include/llvm/CodeGen/SelectionDAG.h
View File

@ -29,7 +29,6 @@
namespace llvm { namespace llvm {
class AliasAnalysis; class AliasAnalysis;
class FunctionLoweringInfo;
class MachineConstantPoolValue; class MachineConstantPoolValue;
class MachineFunction; class MachineFunction;
class MDNode; class MDNode;
@ -134,7 +133,6 @@ class SelectionDAG {
const TargetLowering &TLI; const TargetLowering &TLI;
const TargetSelectionDAGInfo &TSI; const TargetSelectionDAGInfo &TSI;
MachineFunction *MF; MachineFunction *MF;
FunctionLoweringInfo &FLI;
LLVMContext *Context; LLVMContext *Context;
/// EntryNode - The starting token. /// EntryNode - The starting token.
@ -187,7 +185,7 @@ class SelectionDAG {
SelectionDAG(const SelectionDAG&); // Do not implement. SelectionDAG(const SelectionDAG&); // Do not implement.
public: public:
SelectionDAG(const TargetMachine &TM, FunctionLoweringInfo &fli); explicit SelectionDAG(const TargetMachine &TM);
~SelectionDAG(); ~SelectionDAG();
/// init - Prepare this SelectionDAG to process code in the given /// init - Prepare this SelectionDAG to process code in the given
@ -204,7 +202,6 @@ public:
const TargetMachine &getTarget() const { return TM; } const TargetMachine &getTarget() const { return TM; }
const TargetLowering &getTargetLoweringInfo() const { return TLI; } const TargetLowering &getTargetLoweringInfo() const { return TLI; }
const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; } const TargetSelectionDAGInfo &getSelectionDAGInfo() const { return TSI; }
FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }
LLVMContext *getContext() const {return Context; } LLVMContext *getContext() const {return Context; }
/// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'. /// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'.

3
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -74,8 +74,7 @@ FunctionLoweringInfo::FunctionLoweringInfo(const TargetLowering &tli)
: TLI(tli) { : TLI(tli) {
} }
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf, void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
bool EnableFastISel) {
Fn = &fn; Fn = &fn;
MF = &mf; MF = &mf;
RegInfo = &MF->getRegInfo(); RegInfo = &MF->getRegInfo();

2
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
View File

@ -106,7 +106,7 @@ public:
/// set - Initialize this FunctionLoweringInfo with the given Function /// set - Initialize this FunctionLoweringInfo with the given Function
/// and its associated MachineFunction. /// and its associated MachineFunction.
/// ///
void set(const Function &Fn, MachineFunction &MF, bool EnableFastISel); void set(const Function &Fn, MachineFunction &MF);
/// clear - Clear out all the function-specific state. This returns this /// clear - Clear out all the function-specific state. This returns this
/// FunctionLoweringInfo to an empty state, ready to be used for a /// FunctionLoweringInfo to an empty state, ready to be used for a

3
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -790,9 +790,8 @@ unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
} }
// EntryNode could meaningfully have debug info if we can find it... // EntryNode could meaningfully have debug info if we can find it...
SelectionDAG::SelectionDAG(const TargetMachine &tm, FunctionLoweringInfo &fli) SelectionDAG::SelectionDAG(const TargetMachine &tm)
: TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()), : TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()),
FLI(fli),
EntryNode(ISD::EntryToken, DebugLoc(), getVTList(MVT::Other)), EntryNode(ISD::EntryToken, DebugLoc(), getVTList(MVT::Other)),
Root(getEntryNode()), Ordering(0) { Root(getEntryNode()), Ordering(0) {
AllNodes.push_back(&EntryNode); AllNodes.push_back(&EntryNode);

87
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -81,10 +81,6 @@ namespace {
/// registers of some legal type. /// registers of some legal type.
/// ///
struct RegsForValue { struct RegsForValue {
/// TLI - The TargetLowering object.
///
const TargetLowering *TLI;
/// ValueVTs - The value types of the values, which may not be legal, and /// ValueVTs - The value types of the values, which may not be legal, and
/// may need be promoted or synthesized from one or more registers. /// may need be promoted or synthesized from one or more registers.
/// ///
@ -107,25 +103,25 @@ namespace {
/// ///
SmallVector<unsigned, 4> Regs; SmallVector<unsigned, 4> Regs;
RegsForValue() : TLI(0) {} RegsForValue() {}
RegsForValue(const TargetLowering &tli, RegsForValue(const SmallVector<unsigned, 4> &regs,
const SmallVector<unsigned, 4> &regs,
EVT regvt, EVT valuevt) EVT regvt, EVT valuevt)
: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> &regs, RegsForValue(const SmallVector<unsigned, 4> &regs,
const SmallVector<EVT, 4> &regvts, const SmallVector<EVT, 4> &regvts,
const SmallVector<EVT, 4> &valuevts) const SmallVector<EVT, 4> &valuevts)
: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} : ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
RegsForValue(LLVMContext &Context, const TargetLowering &tli, RegsForValue(LLVMContext &Context, const TargetLowering &tli,
unsigned Reg, const Type *Ty) : TLI(&tli) { unsigned Reg, const Type *Ty) {
ComputeValueVTs(tli, Ty, ValueVTs); ComputeValueVTs(tli, Ty, ValueVTs);
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(Context, ValueVT); unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
EVT RegisterVT = TLI->getRegisterType(Context, ValueVT); EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i); Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT); RegVTs.push_back(RegisterVT);
@ -134,19 +130,17 @@ namespace {
} }
/// areValueTypesLegal - Return true if types of all the values are legal. /// areValueTypesLegal - Return true if types of all the values are legal.
bool areValueTypesLegal() { bool areValueTypesLegal(const TargetLowering &TLI) {
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT RegisterVT = RegVTs[Value]; EVT RegisterVT = RegVTs[Value];
if (!TLI->isTypeLegal(RegisterVT)) if (!TLI.isTypeLegal(RegisterVT))
return false; return false;
} }
return true; return true;
} }
/// append - Add the specified values to this one. /// append - Add the specified values to this one.
void append(const RegsForValue &RHS) { void append(const RegsForValue &RHS) {
TLI = RHS.TLI;
ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
Regs.append(RHS.Regs.begin(), RHS.Regs.end()); Regs.append(RHS.Regs.begin(), RHS.Regs.end());
@ -157,7 +151,8 @@ namespace {
/// this value and returns the result as a ValueVTs value. This uses /// this value and returns the result as a ValueVTs value. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag. /// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used. /// If the Flag pointer is NULL, no flag is used.
SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
DebugLoc dl,
SDValue &Chain, SDValue *Flag) const; SDValue &Chain, SDValue *Flag) const;
/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
@ -762,7 +757,7 @@ SDValue SelectionDAGBuilder::getValue(const Value *V) {
RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
SDValue Chain = DAG.getEntryNode(); SDValue Chain = DAG.getEntryNode();
return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
} }
/// Get the EVTs and ArgFlags collections that represent the legalized return /// Get the EVTs and ArgFlags collections that represent the legalized return
@ -829,10 +824,9 @@ static void getReturnInfo(const Type* ReturnType,
void SelectionDAGBuilder::visitRet(const ReturnInst &I) { void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
SDValue Chain = getControlRoot(); SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs; SmallVector<ISD::OutputArg, 8> Outs;
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
if (!FLI.CanLowerReturn) { if (!FuncInfo.CanLowerReturn) {
unsigned DemoteReg = FLI.DemoteRegister; unsigned DemoteReg = FuncInfo.DemoteRegister;
const Function *F = I.getParent()->getParent(); const Function *F = I.getParent()->getParent();
// Emit a store of the return value through the virtual register. // Emit a store of the return value through the virtual register.
@ -4754,15 +4748,19 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
/// this value and returns the result as a ValueVT value. This uses /// this value and returns the result as a ValueVT value. This uses
/// Chain/Flag as the input and updates them for the output Chain/Flag. /// Chain/Flag as the input and updates them for the output Chain/Flag.
/// If the Flag pointer is NULL, no flag is used. /// If the Flag pointer is NULL, no flag is used.
SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
FunctionLoweringInfo &FuncInfo,
DebugLoc dl,
SDValue &Chain, SDValue *Flag) const { SDValue &Chain, SDValue *Flag) const {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// Assemble the legal parts into the final values. // Assemble the legal parts into the final values.
SmallVector<SDValue, 4> Values(ValueVTs.size()); SmallVector<SDValue, 4> Values(ValueVTs.size());
SmallVector<SDValue, 8> Parts; SmallVector<SDValue, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers. // Copy the legal parts from the registers.
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVT); unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
EVT RegisterVT = RegVTs[Value]; EVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs); Parts.resize(NumRegs);
@ -4782,9 +4780,9 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) && if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
RegisterVT.isInteger() && !RegisterVT.isVector()) { RegisterVT.isInteger() && !RegisterVT.isVector()) {
unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister; unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo(); if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
if (FLI.LiveOutRegInfo.size() > SlotNo) { const FunctionLoweringInfo::LiveOutInfo &LOI =
FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[SlotNo]; FuncInfo.LiveOutRegInfo[SlotNo];
unsigned RegSize = RegisterVT.getSizeInBits(); unsigned RegSize = RegisterVT.getSizeInBits();
unsigned NumSignBits = LOI.NumSignBits; unsigned NumSignBits = LOI.NumSignBits;
@ -4837,12 +4835,14 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl,
/// If the Flag pointer is NULL, no flag is used. /// If the Flag pointer is NULL, no flag is used.
void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
SDValue &Chain, SDValue *Flag) const { SDValue &Chain, SDValue *Flag) const {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
// Get the list of the values's legal parts. // Get the list of the values's legal parts.
unsigned NumRegs = Regs.size(); unsigned NumRegs = Regs.size();
SmallVector<SDValue, 8> Parts(NumRegs); SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), ValueVT); unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
EVT RegisterVT = RegVTs[Value]; EVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, dl, getCopyToParts(DAG, dl,
@ -4888,6 +4888,8 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
unsigned MatchingIdx, unsigned MatchingIdx,
SelectionDAG &DAG, SelectionDAG &DAG,
std::vector<SDValue> &Ops) const { std::vector<SDValue> &Ops) const {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
if (HasMatching) if (HasMatching)
Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
@ -4895,7 +4897,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
Ops.push_back(Res); Ops.push_back(Res);
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(*DAG.getContext(), ValueVTs[Value]); unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
EVT RegisterVT = RegVTs[Value]; EVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i) { for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected"); assert(Reg < Regs.size() && "Mismatch in # registers expected");
@ -5155,7 +5157,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
} }
} }
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
return; return;
@ -5173,7 +5175,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
for (; NumRegs; --NumRegs) for (; NumRegs; --NumRegs)
Regs.push_back(RegInfo.createVirtualRegister(RC)); Regs.push_back(RegInfo.createVirtualRegister(RC));
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, RegVT, ValueVT); OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
return; return;
} }
@ -5216,7 +5218,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
for (unsigned i = RegStart; i != RegEnd; ++i) for (unsigned i = RegStart; i != RegEnd; ++i)
Regs.push_back(RegClassRegs[i]); Regs.push_back(RegClassRegs[i]);
OpInfo.AssignedRegs = RegsForValue(TLI, Regs, *RC->vt_begin(), OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
OpInfo.ConstraintVT); OpInfo.ConstraintVT);
OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
return; return;
@ -5498,7 +5500,6 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
} }
RegsForValue MatchedRegs; RegsForValue MatchedRegs;
MatchedRegs.TLI = &TLI;
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
MatchedRegs.RegVTs.push_back(RegVT); MatchedRegs.RegVTs.push_back(RegVT);
@ -5571,7 +5572,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// Copy the input into the appropriate registers. // Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty() || if (OpInfo.AssignedRegs.Regs.empty() ||
!OpInfo.AssignedRegs.areValueTypesLegal()) !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
report_fatal_error("Couldn't allocate input reg for constraint '" + report_fatal_error("Couldn't allocate input reg for constraint '" +
Twine(OpInfo.ConstraintCode) + "'!"); Twine(OpInfo.ConstraintCode) + "'!");
@ -5607,7 +5608,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
// If this asm returns a register value, copy the result from that register // If this asm returns a register value, copy the result from that register
// and set it as the value of the call. // and set it as the value of the call.
if (!RetValRegs.Regs.empty()) { if (!RetValRegs.Regs.empty()) {
SDValue Val = RetValRegs.getCopyFromRegs(DAG, getCurDebugLoc(), SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
Chain, &Flag); Chain, &Flag);
// FIXME: Why don't we do this for inline asms with MRVs? // FIXME: Why don't we do this for inline asms with MRVs?
@ -5647,7 +5648,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
RegsForValue &OutRegs = IndirectStoresToEmit[i].first; RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
const Value *Ptr = IndirectStoresToEmit[i].second; const Value *Ptr = IndirectStoresToEmit[i].second;
SDValue OutVal = OutRegs.getCopyFromRegs(DAG, getCurDebugLoc(), SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
Chain, &Flag); Chain, &Flag);
StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
} }
@ -5905,11 +5906,11 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
SmallVector<ISD::ArgFlagsTy, 4> OutsFlags; SmallVector<ISD::ArgFlagsTy, 4> OutsFlags;
getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
OutVTs, OutsFlags, TLI); OutVTs, OutsFlags, TLI);
FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
FLI.CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(), F.isVarArg(), FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(),
OutVTs, OutsFlags, DAG); F.isVarArg(),
if (!FLI.CanLowerReturn) { OutVTs, OutsFlags, DAG);
if (!FuncInfo->CanLowerReturn) {
// Put in an sret pointer parameter before all the other parameters. // Put in an sret pointer parameter before all the other parameters.
SmallVector<EVT, 1> ValueVTs; SmallVector<EVT, 1> ValueVTs;
ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
@ -6003,7 +6004,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
// Set up the argument values. // Set up the argument values.
unsigned i = 0; unsigned i = 0;
Idx = 1; Idx = 1;
if (!FLI.CanLowerReturn) { if (!FuncInfo->CanLowerReturn) {
// Create a virtual register for the sret pointer, and put in a copy // Create a virtual register for the sret pointer, and put in a copy
// from the sret argument into it. // from the sret argument into it.
SmallVector<EVT, 1> ValueVTs; SmallVector<EVT, 1> ValueVTs;
@ -6017,7 +6018,7 @@ void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
MachineFunction& MF = SDB->DAG.getMachineFunction(); MachineFunction& MF = SDB->DAG.getMachineFunction();
MachineRegisterInfo& RegInfo = MF.getRegInfo(); MachineRegisterInfo& RegInfo = MF.getRegInfo();
unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
FLI.DemoteRegister = SRetReg; FuncInfo->DemoteRegister = SRetReg;
NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
SRetReg, ArgValue); SRetReg, ArgValue);
DAG.setRoot(NewRoot); DAG.setRoot(NewRoot);

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -171,7 +171,7 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) : SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, CodeGenOpt::Level OL) :
MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()), MachineFunctionPass(&ID), TM(tm), TLI(*tm.getTargetLowering()),
FuncInfo(new FunctionLoweringInfo(TLI)), FuncInfo(new FunctionLoweringInfo(TLI)),
CurDAG(new SelectionDAG(tm, *FuncInfo)), CurDAG(new SelectionDAG(tm)),
SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)),
GFI(), GFI(),
OptLevel(OL), OptLevel(OL),
@ -244,7 +244,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n");
CurDAG->init(*MF); CurDAG->init(*MF);
FuncInfo->set(Fn, *MF, EnableFastISel); FuncInfo->set(Fn, *MF);
SDB->init(GFI, *AA); SDB->init(GFI, *AA);
SelectAllBasicBlocks(Fn); SelectAllBasicBlocks(Fn);