6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-27 14:34:58 +00:00
Code Issues Projects Releases Wiki Activity

Add z9 and z10 target processors. Mark z10-only instructions as such.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-07-16 14:05:00 +00:00
parent 71fd2600f4
commit 747052c1a5
5 changed files with 36 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SystemZ/SystemZ.td
View File

@ -18,9 +18,8 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Subtarget Features.
//===----------------------------------------------------------------------===//
def FeatureX
: SubtargetFeature<"dummy", "DummyFeature", "true",
"Some feature">;
def FeatureZ10 : SubtargetFeature<"z10", "HasZ10Insts", "true",
"Support Z10 instructions">;
//===----------------------------------------------------------------------===//
// SystemZ supported processors.
@ -28,7 +27,8 @@ def FeatureX
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"generic", []>;
def : Proc<"z9", []>;
def : Proc<"z10", [FeatureZ10]>;
//===----------------------------------------------------------------------===//
// Register File Description

29
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -11,6 +11,10 @@
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SystemZ Instruction Predicate Definitions.
def IsZ10 : Predicate<"Subtarget.isZ10()">;
include "SystemZInstrFormats.td"
//===----------------------------------------------------------------------===//
@ -406,7 +410,7 @@ def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
"llihh\t{$dst, $src}",
[(set GR64:$dst, i64hh16:$src)]>;
// FIXME: these 3 instructions seem to require extimm facility
def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
"lgfi\t{$dst, $src}",
[(set GR64:$dst, immSExt32:$src)]>;
@ -439,15 +443,19 @@ def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
def MOV8mi : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
"mviy\t{$dst, $src}",
[(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
def MOV16mi : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
"mvhhi\t{$dst, $src}",
[(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>;
[(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>,
Requires<[IsZ10]>;
def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
"mvhi\t{$dst, $src}",
[(store (i32 immSExt16:$src), riaddr:$dst)]>;
[(store (i32 immSExt16:$src), riaddr:$dst)]>,
Requires<[IsZ10]>;
def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
"mvghi\t{$dst, $src}",
[(store (i64 immSExt16:$src), riaddr:$dst)]>;
[(store (i64 immSExt16:$src), riaddr:$dst)]>,
Requires<[IsZ10]>;
// sexts
def MOVSX32rr8 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
@ -634,7 +642,7 @@ def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"oihh\t{$dst, $src2}",
[(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
// FIXME: these 2 instructions seem to require extimm facility
def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
"oilf\t{$dst, $src2}",
[(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
@ -698,15 +706,18 @@ def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
def MUL32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
"mhi\t{$dst, $src2}",
[(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
"msfi\t{$dst, $src2}",
[(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
def MUL64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
"mghi\t{$dst, $src2}",
[(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
"msfi\t{$dst, $src2}",
[(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
Requires<[IsZ10]>;
def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
"msgfi\t{$dst, $src2}",
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
[(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
Requires<[IsZ10]>;
def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
"msy\t{$dst, $src2}",

5
lib/Target/SystemZ/SystemZSubtarget.cpp
View File

@ -19,8 +19,9 @@
using namespace llvm;
SystemZSubtarget::SystemZSubtarget(const TargetMachine &TM, const Module &M,
const std::string &FS) {
std::string CPU = "generic";
const std::string &FS):
HasZ10Insts(false) {
std::string CPU = "z9";
// Parse features string.
ParseSubtargetFeatures(FS, CPU);

9
lib/Target/SystemZ/SystemZSubtarget.h
View File

@ -23,17 +23,20 @@ class Module;
class TargetMachine;
class SystemZSubtarget : public TargetSubtarget {
bool DummyFeature;
bool HasZ10Insts;
public:
/// This constructor initializes the data members to match that
/// of the specified module.
///
SystemZSubtarget(const TargetMachine &TM, const Module &M,
const std::string &FS);
const std::string &FS);
/// ParseSubtargetFeatures - Parses features string setting specified
/// subtarget options. Definition of function is auto generated by tblgen.
std::string ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
std::string ParseSubtargetFeatures(const std::string &FS,
const std::string &CPU);
bool isZ10() const { return HasZ10Insts; }
};
} // End llvm namespace

6
test/CodeGen/SystemZ/05-MemImmStores.ll
View File

@ -1,6 +1,6 @@
; RUN: llvm-as < %s | llc | grep mvghi | count 1
; RUN: llvm-as < %s | llc | grep mvhi | count 1
; RUN: llvm-as < %s | llc | grep mvhhi | count 1
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvghi | count 1
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvhi | count 1
; RUN: llvm-as < %s | llc -mattr=+z10 | grep mvhhi | count 1
; RUN: llvm-as < %s | llc | grep mvi | count 1
target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"