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R600/SI: fix VOP3b encoding v2
v2: document why we hardcode VCC for now. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176099 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -51,6 +51,7 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
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def SIOperand {
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def SIOperand {
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int ZERO = 0x80;
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int ZERO = 0x80;
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int VCC = 0x6A;
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}
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}
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class GPR4Align <RegisterClass rc> : Operand <vAny> {
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class GPR4Align <RegisterClass rc> : Operand <vAny> {
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@ -195,6 +196,29 @@ multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
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: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
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def _e32 : VOP2 <
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op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
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opName#"_e32 $dst, $src0, $src1", pattern
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>;
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def _e64 : VOP3b <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs VReg_32:$dst),
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(ins VSrc_32:$src0, VReg_32:$src1,
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i32imm:$abs, i32imm:$clamp,
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i32imm:$omod, i32imm:$neg),
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opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
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> {
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let SRC2 = SIOperand.ZERO;
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/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
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can write it into any SGPR. We currently don't use the carry out,
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so for now hardcode it to VCC as well */
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let SDST = SIOperand.VCC;
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}
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}
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multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, ValueType vt, PatLeaf cond> {
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string opName, ValueType vt, PatLeaf cond> {
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@ -805,17 +805,19 @@ defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
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//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
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//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
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//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
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//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
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let Defs = [VCC] in { // Carry-out goes to VCC
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let Defs = [VCC] in { // Carry-out goes to VCC
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defm V_ADD_I32 : VOP2_32 <0x00000025, "V_ADD_I32",
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defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
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[(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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[(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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>;
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>;
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defm V_SUB_I32 : VOP2_32 <0x00000026, "V_SUB_I32",
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defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
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[(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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[(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
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>;
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>;
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defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
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let Uses = [VCC] in { // Carry-out comes from VCC
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defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
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defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
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defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>;
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} // End Uses = [VCC]
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} // End Defs = [VCC]
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} // End Defs = [VCC]
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defm V_SUBREV_I32 : VOP2_32 <0x00000027, "V_SUBREV_I32", []>;
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defm V_ADDC_U32 : VOP2_32 <0x00000028, "V_ADDC_U32", []>;
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defm V_SUBB_U32 : VOP2_32 <0x00000029, "V_SUBB_U32", []>;
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defm V_SUBBREV_U32 : VOP2_32 <0x0000002a, "V_SUBBREV_U32", []>;
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defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
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defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
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////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
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////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
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////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
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////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;
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