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[AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125284 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -80,7 +80,9 @@ static SDValue ConcatVectors(SDValue Lower, SDValue Upper, SelectionDAG &DAG);
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/// Generate a DAG to grab 128-bits from a vector > 128 bits. This
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/// sets things up to match to an AVX VEXTRACTF128 instruction or a
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/// simple subregister reference.
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/// simple subregister reference. Idx is an index in the 128 bits we
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/// want. It need not be aligned to a 128-bit bounday. That makes
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/// lowering EXTRACT_VECTOR_ELT operations easier.
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static SDValue Extract128BitVector(SDValue Vec,
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SDValue Idx,
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SelectionDAG &DAG,
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@ -5917,6 +5919,38 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
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if (!isa<ConstantSDNode>(Op.getOperand(1)))
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return SDValue();
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SDValue Vec = Op.getOperand(0);
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EVT VecVT = Vec.getValueType();
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// If this is a 256-bit vector result, first extract the 128-bit
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// vector and then extract from the 128-bit vector.
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if (VecVT.getSizeInBits() > 128) {
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DebugLoc dl = Op.getNode()->getDebugLoc();
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unsigned NumElems = VecVT.getVectorNumElements();
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SDValue Idx = Op.getOperand(1);
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if (!isa<ConstantSDNode>(Idx))
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return SDValue();
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unsigned ExtractNumElems = NumElems / (VecVT.getSizeInBits() / 128);
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unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
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// Get the 128-bit vector.
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bool Upper = IdxVal >= ExtractNumElems;
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Vec = Extract128BitVector(Vec, Idx, DAG, dl);
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// Extract from it.
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SDValue ScaledIdx = Idx;
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if (Upper)
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ScaledIdx = DAG.getNode(ISD::SUB, dl, Idx.getValueType(), Idx,
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DAG.getConstant(ExtractNumElems,
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Idx.getValueType()));
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
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ScaledIdx);
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}
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assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
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if (Subtarget->hasSSE41()) {
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SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
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if (Res.getNode())
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