mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
would have been a Godsend here! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
4d535cadf1
commit
74ab84c31e
@ -48,7 +48,7 @@ class Type;
|
|||||||
/// register, e.g. RAX, EAX, are super-registers of AX.
|
/// register, e.g. RAX, EAX, are super-registers of AX.
|
||||||
///
|
///
|
||||||
struct TargetRegisterDesc {
|
struct TargetRegisterDesc {
|
||||||
const char *Name; // Assembly language name for the register
|
const char *AsmName; // Assembly language name for the register
|
||||||
const char *PrintableName;// Printable name for the reg (for debugging)
|
const char *PrintableName;// Printable name for the reg (for debugging)
|
||||||
const unsigned *AliasSet; // Register Alias Set, described above
|
const unsigned *AliasSet; // Register Alias Set, described above
|
||||||
const unsigned *SubRegs; // Sub-register set, described above
|
const unsigned *SubRegs; // Sub-register set, described above
|
||||||
@ -376,10 +376,10 @@ public:
|
|||||||
return get(RegNo).SuperRegs;
|
return get(RegNo).SuperRegs;
|
||||||
}
|
}
|
||||||
|
|
||||||
/// getName - Return the symbolic target specific name for the specified
|
/// getAsmName - Return the symbolic target specific name for the
|
||||||
/// physical register.
|
/// specified physical register.
|
||||||
const char *getName(unsigned RegNo) const {
|
const char *getAsmName(unsigned RegNo) const {
|
||||||
return get(RegNo).Name;
|
return get(RegNo).AsmName;
|
||||||
}
|
}
|
||||||
|
|
||||||
/// getPrintableName - Return the human-readable symbolic target specific name
|
/// getPrintableName - Return the human-readable symbolic target specific name
|
||||||
|
@ -665,7 +665,7 @@ void LiveRange::dump() const {
|
|||||||
void LiveInterval::print(std::ostream &OS,
|
void LiveInterval::print(std::ostream &OS,
|
||||||
const TargetRegisterInfo *TRI) const {
|
const TargetRegisterInfo *TRI) const {
|
||||||
if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
|
if (TRI && TargetRegisterInfo::isPhysicalRegister(reg))
|
||||||
OS << TRI->getName(reg);
|
OS << TRI->getPrintableName(reg);
|
||||||
else
|
else
|
||||||
OS << "%reg" << reg;
|
OS << "%reg" << reg;
|
||||||
|
|
||||||
|
@ -189,7 +189,7 @@ bool LiveIntervals::conflictsWithPhysRegDef(const LiveInterval &li,
|
|||||||
|
|
||||||
void LiveIntervals::printRegName(unsigned reg) const {
|
void LiveIntervals::printRegName(unsigned reg) const {
|
||||||
if (TargetRegisterInfo::isPhysicalRegister(reg))
|
if (TargetRegisterInfo::isPhysicalRegister(reg))
|
||||||
cerr << tri_->getName(reg);
|
cerr << tri_->getPrintableName(reg);
|
||||||
else
|
else
|
||||||
cerr << "%reg" << reg;
|
cerr << "%reg" << reg;
|
||||||
}
|
}
|
||||||
|
@ -146,7 +146,7 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
|
|||||||
const TargetRegisterInfo *TRI = 0) {
|
const TargetRegisterInfo *TRI = 0) {
|
||||||
if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
|
if (!RegNo || TargetRegisterInfo::isPhysicalRegister(RegNo)) {
|
||||||
if (TRI)
|
if (TRI)
|
||||||
os << " %" << TRI->get(RegNo).Name;
|
os << " %" << TRI->get(RegNo).PrintableName;
|
||||||
else
|
else
|
||||||
os << " %mreg(" << RegNo << ")";
|
os << " %mreg(" << RegNo << ")";
|
||||||
} else
|
} else
|
||||||
|
@ -214,7 +214,7 @@ void MachineFunction::print(std::ostream &OS) const {
|
|||||||
for (MachineRegisterInfo::livein_iterator
|
for (MachineRegisterInfo::livein_iterator
|
||||||
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
|
I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
|
||||||
if (TRI)
|
if (TRI)
|
||||||
OS << " " << TRI->getName(I->first);
|
OS << " " << TRI->getPrintableName(I->first);
|
||||||
else
|
else
|
||||||
OS << " Reg #" << I->first;
|
OS << " Reg #" << I->first;
|
||||||
|
|
||||||
@ -228,7 +228,7 @@ void MachineFunction::print(std::ostream &OS) const {
|
|||||||
for (MachineRegisterInfo::liveout_iterator
|
for (MachineRegisterInfo::liveout_iterator
|
||||||
I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
|
I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
|
||||||
if (TRI)
|
if (TRI)
|
||||||
OS << " " << TRI->getName(*I);
|
OS << " " << TRI->getPrintableName(*I);
|
||||||
else
|
else
|
||||||
OS << " Reg #" << *I;
|
OS << " Reg #" << *I;
|
||||||
OS << "\n";
|
OS << "\n";
|
||||||
|
@ -251,7 +251,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
|
|||||||
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
|
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
|
||||||
for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
|
for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
|
||||||
*ImpUses; ++ImpUses)
|
*ImpUses; ++ImpUses)
|
||||||
DOUT << " -> " << TRI->getName(*ImpUses) << "\n";
|
DOUT << " -> " << TRI->getPrintableName(*ImpUses) << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
if (I.getDesc().getImplicitDefs()) {
|
if (I.getDesc().getImplicitDefs()) {
|
||||||
@ -260,7 +260,7 @@ bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
|
|||||||
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
|
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
|
||||||
for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
|
for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
|
||||||
*ImpDefs; ++ImpDefs)
|
*ImpDefs; ++ImpDefs)
|
||||||
DOUT << " -> " << TRI->getName(*ImpDefs) << "\n";
|
DOUT << " -> " << TRI->getPrintableName(*ImpDefs) << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
//if (TII->hasUnmodelledSideEffects(&I))
|
//if (TII->hasUnmodelledSideEffects(&I))
|
||||||
|
@ -311,7 +311,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
|
|||||||
assert(VirtReg && "Spilling a physical register is illegal!"
|
assert(VirtReg && "Spilling a physical register is illegal!"
|
||||||
" Must not have appropriate kill for the register or use exists beyond"
|
" Must not have appropriate kill for the register or use exists beyond"
|
||||||
" the intended one.");
|
" the intended one.");
|
||||||
DOUT << " Spilling register " << RegInfo->getName(PhysReg)
|
DOUT << " Spilling register " << RegInfo->getPrintableName(PhysReg)
|
||||||
<< " containing %reg" << VirtReg;
|
<< " containing %reg" << VirtReg;
|
||||||
|
|
||||||
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
||||||
@ -535,7 +535,7 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
|
|||||||
markVirtRegModified(VirtReg, false);
|
markVirtRegModified(VirtReg, false);
|
||||||
|
|
||||||
DOUT << " Reloading %reg" << VirtReg << " into "
|
DOUT << " Reloading %reg" << VirtReg << " into "
|
||||||
<< RegInfo->getName(PhysReg) << "\n";
|
<< RegInfo->getPrintableName(PhysReg) << "\n";
|
||||||
|
|
||||||
// Add move instruction(s)
|
// Add move instruction(s)
|
||||||
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
|
TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
|
||||||
@ -646,7 +646,7 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
DOUT << " Regs have values: ";
|
DOUT << " Regs have values: ";
|
||||||
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
|
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
|
||||||
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
||||||
DOUT << "[" << RegInfo->getName(i)
|
DOUT << "[" << RegInfo->getPrintableName(i)
|
||||||
<< ",%reg" << PhysRegsUsed[i] << "] ";
|
<< ",%reg" << PhysRegsUsed[i] << "] ";
|
||||||
DOUT << "\n");
|
DOUT << "\n");
|
||||||
|
|
||||||
@ -700,14 +700,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (PhysReg) {
|
if (PhysReg) {
|
||||||
DOUT << " Last use of " << RegInfo->getName(PhysReg)
|
DOUT << " Last use of " << RegInfo->getPrintableName(PhysReg)
|
||||||
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
||||||
removePhysReg(PhysReg);
|
removePhysReg(PhysReg);
|
||||||
for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
|
for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
|
||||||
*AliasSet; ++AliasSet) {
|
*AliasSet; ++AliasSet) {
|
||||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||||
DOUT << " Last use of "
|
DOUT << " Last use of "
|
||||||
<< RegInfo->getName(*AliasSet)
|
<< RegInfo->getPrintableName(*AliasSet)
|
||||||
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
||||||
removePhysReg(*AliasSet);
|
removePhysReg(*AliasSet);
|
||||||
}
|
}
|
||||||
@ -806,14 +806,14 @@ void RABigBlock::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (PhysReg) {
|
if (PhysReg) {
|
||||||
DOUT << " Register " << RegInfo->getName(PhysReg)
|
DOUT << " Register " << RegInfo->getPrintableName(PhysReg)
|
||||||
<< " [%reg" << VirtReg
|
<< " [%reg" << VirtReg
|
||||||
<< "] is never used, removing it frame live list\n";
|
<< "] is never used, removing it frame live list\n";
|
||||||
removePhysReg(PhysReg);
|
removePhysReg(PhysReg);
|
||||||
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
|
for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
|
||||||
*AliasSet; ++AliasSet) {
|
*AliasSet; ++AliasSet) {
|
||||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||||
DOUT << " Register " << RegInfo->getName(*AliasSet)
|
DOUT << " Register " << RegInfo->getPrintableName(*AliasSet)
|
||||||
<< " [%reg" << *AliasSet
|
<< " [%reg" << *AliasSet
|
||||||
<< "] is never used, removing it frame live list\n";
|
<< "] is never used, removing it frame live list\n";
|
||||||
removePhysReg(*AliasSet);
|
removePhysReg(*AliasSet);
|
||||||
|
@ -164,7 +164,7 @@ namespace {
|
|||||||
if (TargetRegisterInfo::isVirtualRegister(reg)) {
|
if (TargetRegisterInfo::isVirtualRegister(reg)) {
|
||||||
reg = vrm_->getPhys(reg);
|
reg = vrm_->getPhys(reg);
|
||||||
}
|
}
|
||||||
DOUT << tri_->getName(reg) << '\n';
|
DOUT << tri_->getPrintableName(reg) << '\n';
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
@ -239,7 +239,8 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
|
|||||||
|
|
||||||
// Try to coalesce.
|
// Try to coalesce.
|
||||||
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
|
if (!li_->conflictsWithPhysRegDef(cur, *vrm_, SrcReg)) {
|
||||||
DOUT << "Coalescing: " << cur << " -> " << tri_->getName(SrcReg) << '\n';
|
DOUT << "Coalescing: " << cur << " -> " << tri_->getPrintableName(SrcReg)
|
||||||
|
<< '\n';
|
||||||
vrm_->clearVirt(cur.reg);
|
vrm_->clearVirt(cur.reg);
|
||||||
vrm_->assignVirt2Phys(cur.reg, SrcReg);
|
vrm_->assignVirt2Phys(cur.reg, SrcReg);
|
||||||
++NumCoalesce;
|
++NumCoalesce;
|
||||||
@ -627,7 +628,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
|
|||||||
// the free physical register and add this interval to the active
|
// the free physical register and add this interval to the active
|
||||||
// list.
|
// list.
|
||||||
if (physReg) {
|
if (physReg) {
|
||||||
DOUT << tri_->getName(physReg) << '\n';
|
DOUT << tri_->getPrintableName(physReg) << '\n';
|
||||||
vrm_->assignVirt2Phys(cur->reg, physReg);
|
vrm_->assignVirt2Phys(cur->reg, physReg);
|
||||||
prt_->addRegUse(physReg);
|
prt_->addRegUse(physReg);
|
||||||
active_.push_back(std::make_pair(cur, cur->begin()));
|
active_.push_back(std::make_pair(cur, cur->begin()));
|
||||||
@ -689,7 +690,7 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
|
|||||||
}
|
}
|
||||||
|
|
||||||
DOUT << "\t\tregister with min weight: "
|
DOUT << "\t\tregister with min weight: "
|
||||||
<< tri_->getName(minReg) << " (" << minWeight << ")\n";
|
<< tri_->getPrintableName(minReg) << " (" << minWeight << ")\n";
|
||||||
|
|
||||||
// if the current has the minimum weight, we need to spill it and
|
// if the current has the minimum weight, we need to spill it and
|
||||||
// add any added intervals back to unhandled, and restart
|
// add any added intervals back to unhandled, and restart
|
||||||
@ -868,11 +869,11 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
|
|||||||
if (cur->preference) {
|
if (cur->preference) {
|
||||||
if (prt_->isRegAvail(cur->preference)) {
|
if (prt_->isRegAvail(cur->preference)) {
|
||||||
DOUT << "\t\tassigned the preferred register: "
|
DOUT << "\t\tassigned the preferred register: "
|
||||||
<< tri_->getName(cur->preference) << "\n";
|
<< tri_->getPrintableName(cur->preference) << "\n";
|
||||||
return cur->preference;
|
return cur->preference;
|
||||||
} else
|
} else
|
||||||
DOUT << "\t\tunable to assign the preferred register: "
|
DOUT << "\t\tunable to assign the preferred register: "
|
||||||
<< tri_->getName(cur->preference) << "\n";
|
<< tri_->getPrintableName(cur->preference) << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
// Scan for the first available register.
|
// Scan for the first available register.
|
||||||
|
@ -286,7 +286,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
|
|||||||
assert(VirtReg && "Spilling a physical register is illegal!"
|
assert(VirtReg && "Spilling a physical register is illegal!"
|
||||||
" Must not have appropriate kill for the register or use exists beyond"
|
" Must not have appropriate kill for the register or use exists beyond"
|
||||||
" the intended one.");
|
" the intended one.");
|
||||||
DOUT << " Spilling register " << TRI->getName(PhysReg)
|
DOUT << " Spilling register " << TRI->getPrintableName(PhysReg)
|
||||||
<< " containing %reg" << VirtReg;
|
<< " containing %reg" << VirtReg;
|
||||||
|
|
||||||
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
||||||
@ -502,7 +502,7 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
|
|||||||
markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
|
markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
|
||||||
|
|
||||||
DOUT << " Reloading %reg" << VirtReg << " into "
|
DOUT << " Reloading %reg" << VirtReg << " into "
|
||||||
<< TRI->getName(PhysReg) << "\n";
|
<< TRI->getPrintableName(PhysReg) << "\n";
|
||||||
|
|
||||||
// Add move instruction(s)
|
// Add move instruction(s)
|
||||||
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
|
||||||
@ -575,7 +575,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
DOUT << " Regs have values: ";
|
DOUT << " Regs have values: ";
|
||||||
for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
|
for (unsigned i = 0; i != TRI->getNumRegs(); ++i)
|
||||||
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
|
||||||
DOUT << "[" << TRI->getName(i)
|
DOUT << "[" << TRI->getPrintableName(i)
|
||||||
<< ",%reg" << PhysRegsUsed[i] << "] ";
|
<< ",%reg" << PhysRegsUsed[i] << "] ";
|
||||||
DOUT << "\n");
|
DOUT << "\n");
|
||||||
|
|
||||||
@ -637,14 +637,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (PhysReg) {
|
if (PhysReg) {
|
||||||
DOUT << " Last use of " << TRI->getName(PhysReg)
|
DOUT << " Last use of " << TRI->getPrintableName(PhysReg)
|
||||||
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
||||||
removePhysReg(PhysReg);
|
removePhysReg(PhysReg);
|
||||||
for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
|
for (const unsigned *AliasSet = TRI->getSubRegisters(PhysReg);
|
||||||
*AliasSet; ++AliasSet) {
|
*AliasSet; ++AliasSet) {
|
||||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||||
DOUT << " Last use of "
|
DOUT << " Last use of "
|
||||||
<< TRI->getName(*AliasSet)
|
<< TRI->getPrintableName(*AliasSet)
|
||||||
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
<< "[%reg" << VirtReg <<"], removing it from live set\n";
|
||||||
removePhysReg(*AliasSet);
|
removePhysReg(*AliasSet);
|
||||||
}
|
}
|
||||||
@ -728,7 +728,7 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
MF->getRegInfo().setPhysRegUsed(DestPhysReg);
|
||||||
markVirtRegModified(DestVirtReg);
|
markVirtRegModified(DestVirtReg);
|
||||||
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
|
getVirtRegLastUse(DestVirtReg) = std::make_pair((MachineInstr*)0, 0);
|
||||||
DOUT << " Assigning " << TRI->getName(DestPhysReg)
|
DOUT << " Assigning " << TRI->getPrintableName(DestPhysReg)
|
||||||
<< " to %reg" << DestVirtReg << "\n";
|
<< " to %reg" << DestVirtReg << "\n";
|
||||||
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
|
MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
|
||||||
}
|
}
|
||||||
@ -751,14 +751,14 @@ void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (PhysReg) {
|
if (PhysReg) {
|
||||||
DOUT << " Register " << TRI->getName(PhysReg)
|
DOUT << " Register " << TRI->getPrintableName(PhysReg)
|
||||||
<< " [%reg" << VirtReg
|
<< " [%reg" << VirtReg
|
||||||
<< "] is never used, removing it frame live list\n";
|
<< "] is never used, removing it frame live list\n";
|
||||||
removePhysReg(PhysReg);
|
removePhysReg(PhysReg);
|
||||||
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
|
for (const unsigned *AliasSet = TRI->getAliasSet(PhysReg);
|
||||||
*AliasSet; ++AliasSet) {
|
*AliasSet; ++AliasSet) {
|
||||||
if (PhysRegsUsed[*AliasSet] != -2) {
|
if (PhysRegsUsed[*AliasSet] != -2) {
|
||||||
DOUT << " Register " << TRI->getName(*AliasSet)
|
DOUT << " Register " << TRI->getPrintableName(*AliasSet)
|
||||||
<< " [%reg" << *AliasSet
|
<< " [%reg" << *AliasSet
|
||||||
<< "] is never used, removing it frame live list\n";
|
<< "] is never used, removing it frame live list\n";
|
||||||
removePhysReg(*AliasSet);
|
removePhysReg(*AliasSet);
|
||||||
|
@ -4181,7 +4181,8 @@ void SDNode::dump(const SelectionDAG *G) const {
|
|||||||
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
|
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(this)) {
|
||||||
if (G && R->getReg() &&
|
if (G && R->getReg() &&
|
||||||
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
|
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
|
||||||
cerr << " " <<G->getTarget().getRegisterInfo()->getName(R->getReg());
|
cerr << " "
|
||||||
|
<< G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
|
||||||
} else {
|
} else {
|
||||||
cerr << " #" << R->getReg();
|
cerr << " #" << R->getReg();
|
||||||
}
|
}
|
||||||
|
@ -133,7 +133,8 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
|
|||||||
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
|
} else if (const RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node)) {
|
||||||
if (G && R->getReg() != 0 &&
|
if (G && R->getReg() != 0 &&
|
||||||
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
|
TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
|
||||||
Op = Op + " " + G->getTarget().getRegisterInfo()->getName(R->getReg());
|
Op = Op + " " +
|
||||||
|
G->getTarget().getRegisterInfo()->getPrintableName(R->getReg());
|
||||||
} else {
|
} else {
|
||||||
Op += " #" + utostr(R->getReg());
|
Op += " #" + utostr(R->getReg());
|
||||||
}
|
}
|
||||||
|
@ -1648,7 +1648,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint,
|
|||||||
|
|
||||||
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
|
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
|
||||||
I != E; ++I) {
|
I != E; ++I) {
|
||||||
if (StringsEqualNoCase(RegName, RI->get(*I).Name))
|
if (StringsEqualNoCase(RegName, RI->get(*I).AsmName))
|
||||||
return std::make_pair(*I, RC);
|
return std::make_pair(*I, RC);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -1537,7 +1537,7 @@ void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
|
|||||||
|
|
||||||
void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
|
void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
|
||||||
if (TargetRegisterInfo::isPhysicalRegister(reg))
|
if (TargetRegisterInfo::isPhysicalRegister(reg))
|
||||||
cerr << tri_->getName(reg);
|
cerr << tri_->getPrintableName(reg);
|
||||||
else
|
else
|
||||||
cerr << "%reg" << reg;
|
cerr << "%reg" << reg;
|
||||||
}
|
}
|
||||||
|
@ -141,8 +141,8 @@ void VirtRegMap::print(std::ostream &OS) const {
|
|||||||
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
|
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
|
||||||
e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
|
e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
|
||||||
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
|
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
|
||||||
OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i]) << "]\n";
|
OS << "[reg" << i << " -> " << TRI->getPrintableName(Virt2PhysMap[i])
|
||||||
|
<< "]\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
|
for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
|
||||||
@ -351,7 +351,7 @@ public:
|
|||||||
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
|
DOUT << "Remembering RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1;
|
||||||
else
|
else
|
||||||
DOUT << "Remembering SS#" << SlotOrReMat;
|
DOUT << "Remembering SS#" << SlotOrReMat;
|
||||||
DOUT << " in physreg " << TRI->getName(Reg) << "\n";
|
DOUT << " in physreg " << TRI->getPrintableName(Reg) << "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
/// canClobberPhysReg - Return true if the spiller is allowed to change the
|
/// canClobberPhysReg - Return true if the spiller is allowed to change the
|
||||||
@ -392,7 +392,7 @@ void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
|
|||||||
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
||||||
"Bidirectional map mismatch!");
|
"Bidirectional map mismatch!");
|
||||||
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
|
SpillSlotsOrReMatsAvailable[SlotOrReMat] &= ~1;
|
||||||
DOUT << "PhysReg " << TRI->getName(PhysReg)
|
DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
|
||||||
<< " copied, it is available for use but can no longer be modified\n";
|
<< " copied, it is available for use but can no longer be modified\n";
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -417,7 +417,7 @@ void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
|
|||||||
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
assert((SpillSlotsOrReMatsAvailable[SlotOrReMat] >> 1) == PhysReg &&
|
||||||
"Bidirectional map mismatch!");
|
"Bidirectional map mismatch!");
|
||||||
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
|
SpillSlotsOrReMatsAvailable.erase(SlotOrReMat);
|
||||||
DOUT << "PhysReg " << TRI->getName(PhysReg)
|
DOUT << "PhysReg " << TRI->getPrintableName(PhysReg)
|
||||||
<< " clobbered, invalidating ";
|
<< " clobbered, invalidating ";
|
||||||
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
|
if (SlotOrReMat > VirtRegMap::MAX_STACK_SLOT)
|
||||||
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
|
DOUT << "RM#" << SlotOrReMat-VirtRegMap::MAX_STACK_SLOT-1 << "\n";
|
||||||
@ -1135,9 +1135,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
|||||||
else
|
else
|
||||||
DOUT << "Reusing SS#" << ReuseSlot;
|
DOUT << "Reusing SS#" << ReuseSlot;
|
||||||
DOUT << " from physreg "
|
DOUT << " from physreg "
|
||||||
<< TRI->getName(PhysReg) << " for vreg"
|
<< TRI->getPrintableName(PhysReg) << " for vreg"
|
||||||
<< VirtReg <<" instead of reloading into physreg "
|
<< VirtReg <<" instead of reloading into physreg "
|
||||||
<< TRI->getName(VRM.getPhys(VirtReg)) << "\n";
|
<< TRI->getPrintableName(VRM.getPhys(VirtReg)) << "\n";
|
||||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||||
MI.getOperand(i).setReg(RReg);
|
MI.getOperand(i).setReg(RReg);
|
||||||
|
|
||||||
@ -1208,8 +1208,8 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
|||||||
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
|
DOUT << "Reusing RM#" << ReuseSlot-VirtRegMap::MAX_STACK_SLOT-1;
|
||||||
else
|
else
|
||||||
DOUT << "Reusing SS#" << ReuseSlot;
|
DOUT << "Reusing SS#" << ReuseSlot;
|
||||||
DOUT << " from physreg " << TRI->getName(PhysReg) << " for vreg"
|
DOUT << " from physreg " << TRI->getPrintableName(PhysReg)
|
||||||
<< VirtReg
|
<< " for vreg" << VirtReg
|
||||||
<< " instead of reloading into same physreg.\n";
|
<< " instead of reloading into same physreg.\n";
|
||||||
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
unsigned RReg = SubIdx ? TRI->getSubReg(PhysReg, SubIdx) : PhysReg;
|
||||||
MI.getOperand(i).setReg(RReg);
|
MI.getOperand(i).setReg(RReg);
|
||||||
|
@ -273,7 +273,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
|
|||||||
switch (MO.getType()) {
|
switch (MO.getType()) {
|
||||||
case MachineOperand::MO_Register:
|
case MachineOperand::MO_Register:
|
||||||
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
else
|
else
|
||||||
assert(0 && "not implemented");
|
assert(0 && "not implemented");
|
||||||
break;
|
break;
|
||||||
@ -393,7 +393,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
|
|||||||
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
||||||
|
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
||||||
O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
|
|
||||||
// Print the shift opc.
|
// Print the shift opc.
|
||||||
O << ", "
|
O << ", "
|
||||||
@ -402,7 +402,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
|
|||||||
|
|
||||||
if (MO2.getReg()) {
|
if (MO2.getReg()) {
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
|
assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
|
||||||
O << TM.getRegisterInfo()->get(MO2.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
|
||||||
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
|
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
|
||||||
} else {
|
} else {
|
||||||
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
|
O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
|
||||||
@ -419,7 +419,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
|
|
||||||
if (!MO2.getReg()) {
|
if (!MO2.getReg()) {
|
||||||
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
|
if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
|
||||||
@ -432,7 +432,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
|
|||||||
|
|
||||||
O << ", "
|
O << ", "
|
||||||
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
<< (char)ARM_AM::getAM2Op(MO3.getImm())
|
||||||
<< TM.getRegisterInfo()->get(MO2.getReg()).Name;
|
<< TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
|
||||||
|
|
||||||
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
|
||||||
O << ", "
|
O << ", "
|
||||||
@ -455,7 +455,7 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
|
|||||||
}
|
}
|
||||||
|
|
||||||
O << (char)ARM_AM::getAM2Op(MO2.getImm())
|
O << (char)ARM_AM::getAM2Op(MO2.getImm())
|
||||||
<< TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
<< TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
|
|
||||||
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
|
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
|
||||||
O << ", "
|
O << ", "
|
||||||
@ -469,12 +469,12 @@ void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
|
|||||||
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
const MachineOperand &MO3 = MI->getOperand(Op+2);
|
||||||
|
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
|
|
||||||
if (MO2.getReg()) {
|
if (MO2.getReg()) {
|
||||||
O << ", "
|
O << ", "
|
||||||
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
<< (char)ARM_AM::getAM3Op(MO3.getImm())
|
||||||
<< TM.getRegisterInfo()->get(MO2.getReg()).Name
|
<< TM.getRegisterInfo()->get(MO2.getReg()).AsmName
|
||||||
<< "]";
|
<< "]";
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -492,7 +492,7 @@ void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
|
|||||||
|
|
||||||
if (MO1.getReg()) {
|
if (MO1.getReg()) {
|
||||||
O << (char)ARM_AM::getAM3Op(MO2.getImm())
|
O << (char)ARM_AM::getAM3Op(MO2.getImm())
|
||||||
<< TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
<< TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -545,13 +545,13 @@ void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
|
|||||||
return;
|
return;
|
||||||
} else if (Modifier && strcmp(Modifier, "base") == 0) {
|
} else if (Modifier && strcmp(Modifier, "base") == 0) {
|
||||||
// Used for FSTM{D|S} and LSTM{D|S} operations.
|
// Used for FSTM{D|S} and LSTM{D|S} operations.
|
||||||
O << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
|
if (ARM_AM::getAM5WBFlag(MO2.getImm()))
|
||||||
O << "!";
|
O << "!";
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
|
|
||||||
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
|
if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
|
||||||
O << ", #"
|
O << ", #"
|
||||||
@ -570,15 +570,15 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
|
|||||||
|
|
||||||
const MachineOperand &MO1 = MI->getOperand(Op);
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
|
||||||
O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).Name << "]";
|
O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
|
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
|
||||||
const MachineOperand &MO1 = MI->getOperand(Op);
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
||||||
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).Name << "]";
|
O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
void
|
||||||
@ -593,9 +593,9 @@ ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
if (MO3.getReg())
|
if (MO3.getReg())
|
||||||
O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).Name;
|
O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
|
||||||
else if (unsigned ImmOffs = MO2.getImm()) {
|
else if (unsigned ImmOffs = MO2.getImm()) {
|
||||||
O << ", #" << ImmOffs;
|
O << ", #" << ImmOffs;
|
||||||
if (Scale > 1)
|
if (Scale > 1)
|
||||||
@ -620,7 +620,7 @@ ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
|
|||||||
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
|
void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
|
||||||
const MachineOperand &MO1 = MI->getOperand(Op);
|
const MachineOperand &MO1 = MI->getOperand(Op);
|
||||||
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
||||||
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).Name;
|
O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
|
||||||
if (unsigned ImmOffs = MO2.getImm())
|
if (unsigned ImmOffs = MO2.getImm())
|
||||||
O << ", #" << ImmOffs << " * 4";
|
O << ", #" << ImmOffs << " * 4";
|
||||||
O << "]";
|
O << "]";
|
||||||
|
@ -77,7 +77,7 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
|
|||||||
if (MO.getType() == MachineOperand::MO_Register) {
|
if (MO.getType() == MachineOperand::MO_Register) {
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
||||||
"Not physreg??");
|
"Not physreg??");
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
} else if (MO.isImmediate()) {
|
} else if (MO.isImmediate()) {
|
||||||
O << MO.getImm();
|
O << MO.getImm();
|
||||||
assert(MO.getImm() < (1 << 30));
|
assert(MO.getImm() < (1 << 30));
|
||||||
@ -92,7 +92,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) {
|
|||||||
|
|
||||||
switch (MO.getType()) {
|
switch (MO.getType()) {
|
||||||
case MachineOperand::MO_Register:
|
case MachineOperand::MO_Register:
|
||||||
O << RI.get(MO.getReg()).Name;
|
O << RI.get(MO.getReg()).AsmName;
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case MachineOperand::MO_Immediate:
|
case MachineOperand::MO_Immediate:
|
||||||
|
@ -334,6 +334,6 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|||||||
|
|
||||||
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
|
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
|
||||||
{
|
{
|
||||||
std::string s(RegisterDescriptors[reg].Name);
|
std::string s(RegisterDescriptors[reg].PrintableName);
|
||||||
return s;
|
return s;
|
||||||
}
|
}
|
||||||
|
@ -75,14 +75,14 @@ namespace {
|
|||||||
unsigned RegNo = MO.getReg();
|
unsigned RegNo = MO.getReg();
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
|
assert(TargetRegisterInfo::isPhysicalRegister(RegNo) &&
|
||||||
"Not physreg??");
|
"Not physreg??");
|
||||||
O << TM.getRegisterInfo()->get(RegNo).Name;
|
O << TM.getRegisterInfo()->get(RegNo).AsmName;
|
||||||
}
|
}
|
||||||
|
|
||||||
void printOperand(const MachineInstr *MI, unsigned OpNo) {
|
void printOperand(const MachineInstr *MI, unsigned OpNo) {
|
||||||
const MachineOperand &MO = MI->getOperand(OpNo);
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
||||||
if (MO.isRegister()) {
|
if (MO.isRegister()) {
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
|
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
} else if (MO.isImmediate()) {
|
} else if (MO.isImmediate()) {
|
||||||
O << MO.getImm();
|
O << MO.getImm();
|
||||||
} else {
|
} else {
|
||||||
@ -149,7 +149,7 @@ namespace {
|
|||||||
// the value contained in the register. For this reason, the darwin
|
// the value contained in the register. For this reason, the darwin
|
||||||
// assembler requires that we print r0 as 0 (no r) when used as the base.
|
// assembler requires that we print r0 as 0 (no r) when used as the base.
|
||||||
const MachineOperand &MO = MI->getOperand(OpNo);
|
const MachineOperand &MO = MI->getOperand(OpNo);
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
O << ", ";
|
O << ", ";
|
||||||
printOperand(MI, OpNo+1);
|
printOperand(MI, OpNo+1);
|
||||||
}
|
}
|
||||||
|
@ -56,7 +56,7 @@ namespace {
|
|||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
||||||
"Not physref??");
|
"Not physref??");
|
||||||
//XXX Bug Workaround: See note in Printer::doInitialization about %.
|
//XXX Bug Workaround: See note in Printer::doInitialization about %.
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
} else {
|
} else {
|
||||||
printOp(MO);
|
printOp(MO);
|
||||||
}
|
}
|
||||||
@ -168,7 +168,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
|
|||||||
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
|
const TargetRegisterInfo &RI = *TM.getRegisterInfo();
|
||||||
switch (MO.getType()) {
|
switch (MO.getType()) {
|
||||||
case MachineOperand::MO_Register:
|
case MachineOperand::MO_Register:
|
||||||
O << RI.get(MO.getReg()).Name;
|
O << RI.get(MO.getReg()).AsmName;
|
||||||
return;
|
return;
|
||||||
|
|
||||||
case MachineOperand::MO_Immediate:
|
case MachineOperand::MO_Immediate:
|
||||||
|
@ -169,9 +169,9 @@ emitFrameDirective(MachineFunction &MF)
|
|||||||
unsigned stackSize = MF.getFrameInfo()->getStackSize();
|
unsigned stackSize = MF.getFrameInfo()->getStackSize();
|
||||||
|
|
||||||
|
|
||||||
O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).Name)
|
O << "\t.frame\t" << "$" << LowercaseString(RI.get(stackReg).AsmName)
|
||||||
<< "," << stackSize << ","
|
<< "," << stackSize << ","
|
||||||
<< "$" << LowercaseString(RI.get(returnReg).Name)
|
<< "$" << LowercaseString(RI.get(returnReg).AsmName)
|
||||||
<< "\n";
|
<< "\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -365,7 +365,7 @@ printOperand(const MachineInstr *MI, int opNum)
|
|||||||
{
|
{
|
||||||
case MachineOperand::MO_Register:
|
case MachineOperand::MO_Register:
|
||||||
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
||||||
O << "$" << LowercaseString (RI.get(MO.getReg()).Name);
|
O << "$" << LowercaseString (RI.get(MO.getReg()).AsmName);
|
||||||
else
|
else
|
||||||
O << "$" << MO.getReg();
|
O << "$" << MO.getReg();
|
||||||
break;
|
break;
|
||||||
|
@ -113,7 +113,7 @@ namespace {
|
|||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
const char *RegName = TM.getRegisterInfo()->get(RegNo).Name;
|
const char *RegName = TM.getRegisterInfo()->get(RegNo).AsmName;
|
||||||
// Linux assembler (Others?) does not take register mnemonics.
|
// Linux assembler (Others?) does not take register mnemonics.
|
||||||
// FIXME - What about special registers used in mfspr/mtspr?
|
// FIXME - What about special registers used in mfspr/mtspr?
|
||||||
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
|
if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
|
||||||
|
@ -22,7 +22,7 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
|
|||||||
}
|
}
|
||||||
|
|
||||||
// GP8 - One of the 32 64-bit general-purpose registers
|
// GP8 - One of the 32 64-bit general-purpose registers
|
||||||
class GP8<GPR SubReg, string n> : PPCReg<SubReg.Name> {
|
class GP8<GPR SubReg, string n> : PPCReg<SubReg.AsmName> {
|
||||||
field bits<5> Num = SubReg.Num;
|
field bits<5> Num = SubReg.Num;
|
||||||
let SubRegs = [SubReg];
|
let SubRegs = [SubReg];
|
||||||
let PrintableName = n;
|
let PrintableName = n;
|
||||||
|
@ -146,7 +146,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
|
|||||||
switch (MO.getType()) {
|
switch (MO.getType()) {
|
||||||
case MachineOperand::MO_Register:
|
case MachineOperand::MO_Register:
|
||||||
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
|
||||||
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
|
O << "%" << LowercaseString (RI.get(MO.getReg()).AsmName);
|
||||||
else
|
else
|
||||||
O << "%reg" << MO.getReg();
|
O << "%reg" << MO.getReg();
|
||||||
break;
|
break;
|
||||||
|
@ -25,7 +25,7 @@ class RegisterClass; // Forward def
|
|||||||
// in the target machine. String n will become the "name" of the register.
|
// in the target machine. String n will become the "name" of the register.
|
||||||
class Register<string n> {
|
class Register<string n> {
|
||||||
string Namespace = "";
|
string Namespace = "";
|
||||||
string Name = n;
|
string AsmName = n;
|
||||||
string PrintableName = n;
|
string PrintableName = n;
|
||||||
|
|
||||||
// SpillSize - If this value is set to a non-zero value, it is the size in
|
// SpillSize - If this value is set to a non-zero value, it is the size in
|
||||||
|
@ -229,7 +229,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
|
|||||||
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
|
((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8));
|
||||||
Reg = getX86SubSuperRegister(Reg, VT);
|
Reg = getX86SubSuperRegister(Reg, VT);
|
||||||
}
|
}
|
||||||
for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
|
for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
|
||||||
O << (char)tolower(*Name);
|
O << (char)tolower(*Name);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -575,7 +575,7 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO,
|
|||||||
}
|
}
|
||||||
|
|
||||||
O << '%';
|
O << '%';
|
||||||
for (const char *Name = RI.get(Reg).Name; *Name; ++Name)
|
for (const char *Name = RI.get(Reg).AsmName; *Name; ++Name)
|
||||||
O << (char)tolower(*Name);
|
O << (char)tolower(*Name);
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
@ -125,7 +125,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
|
|||||||
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
|
((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8));
|
||||||
Reg = getX86SubSuperRegister(Reg, VT);
|
Reg = getX86SubSuperRegister(Reg, VT);
|
||||||
}
|
}
|
||||||
O << RI.get(Reg).Name;
|
O << RI.get(Reg).AsmName;
|
||||||
} else
|
} else
|
||||||
O << "reg" << MO.getReg();
|
O << "reg" << MO.getReg();
|
||||||
return;
|
return;
|
||||||
@ -271,7 +271,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
O << '%' << RI.get(Reg).Name;
|
O << '%' << RI.get(Reg).AsmName;
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -43,7 +43,7 @@ struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public X86SharedAsmPrinter {
|
|||||||
if (MO.isRegister()) {
|
if (MO.isRegister()) {
|
||||||
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
|
||||||
"Not physreg??");
|
"Not physreg??");
|
||||||
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
|
O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
|
||||||
} else {
|
} else {
|
||||||
printOp(MO, Modifier);
|
printOp(MO, Modifier);
|
||||||
}
|
}
|
||||||
|
@ -520,8 +520,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
|
|||||||
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
||||||
const CodeGenRegister &Reg = Registers[i];
|
const CodeGenRegister &Reg = Registers[i];
|
||||||
OS << " { \"";
|
OS << " { \"";
|
||||||
if (!Reg.TheDef->getValueAsString("Name").empty())
|
if (!Reg.TheDef->getValueAsString("AsmName").empty())
|
||||||
OS << Reg.TheDef->getValueAsString("Name");
|
OS << Reg.TheDef->getValueAsString("AsmName");
|
||||||
else
|
else
|
||||||
OS << Reg.getName();
|
OS << Reg.getName();
|
||||||
OS << "\",\t\"";
|
OS << "\",\t\"";
|
||||||
|
Loading…
Reference in New Issue
Block a user