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updated patch for the ARM fused multiply add/sub
In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -38,9 +38,9 @@ def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable NEON instructions",
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[FeatureVFP3]>;
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def FeatureNEONVFP4 : SubtargetFeature<"neon-vfpv4", "HasNEONVFPv4", "true",
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"Enable NEON-VFP4 instructions",
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[FeatureVFP4, FeatureNEON]>;
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def FeatureNEON2 : SubtargetFeature<"neon2", "HasNEON2", "true",
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"Enable Advanced SIMD2 instructions",
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[FeatureNEON]>;
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def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
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"Enable Thumb2 instructions">;
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def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
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@@ -76,6 +76,8 @@ def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
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def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
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"true",
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"Use NEON for single precision FP">;
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// Allow more precision in FP computation
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def FPContractions : Predicate<"!TM.Options.NoExcessFPPrecision">;
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// Disable 32-bit to 16-bit narrowing for experimentation.
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def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
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