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ARM: support PIC on Windows on ARM
Handle lowering of global addresses for PIC mode compilation on Windows. Always use the movw/movt load to load the address as Windows on ARM requires ARMv7+ and is a pure Thumb environment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208385 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2485,6 +2485,23 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
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return Result;
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return Result;
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}
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}
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SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
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SelectionDAG &DAG) const {
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assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
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assert(Subtarget->useMovt() && "Windows on ARM expects to use movw/movt");
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const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
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EVT PtrVT = getPointerTy();
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SDLoc DL(Op);
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++NumMovwMovt;
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// FIXME: Once remat is capable of dealing with instructions with register
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// operands, expand this into two nodes.
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return DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
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DAG.getTargetGlobalAddress(GV, DL, PtrVT));
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}
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SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
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SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
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SelectionDAG &DAG) const {
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SelectionDAG &DAG) const {
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assert(Subtarget->isTargetELF() &&
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assert(Subtarget->isTargetELF() &&
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@ -6050,8 +6067,15 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
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case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
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case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
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case ISD::GlobalAddress:
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case ISD::GlobalAddress:
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return Subtarget->isTargetMachO() ? LowerGlobalAddressDarwin(Op, DAG) :
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switch (Subtarget->getTargetTriple().getObjectFormat()) {
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LowerGlobalAddressELF(Op, DAG);
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default: llvm_unreachable("unknown object format");
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case Triple::COFF:
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return LowerGlobalAddressWindows(Op, DAG);
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case Triple::ELF:
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return LowerGlobalAddressELF(Op, DAG);
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case Triple::MachO:
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return LowerGlobalAddressDarwin(Op, DAG);
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}
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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@ -437,6 +437,7 @@ namespace llvm {
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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SelectionDAG &DAG) const;
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SelectionDAG &DAG) const;
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16
test/CodeGen/ARM/Windows/pic.ll
Normal file
16
test/CodeGen/ARM/Windows/pic.ll
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@ -0,0 +1,16 @@
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; RUN: llc -mtriple thumbv7-windows-itanium -relocation-model pic -filetype asm -o - %s \
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; RUN: | FileCheck %s
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@external = external global i8
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define arm_aapcs_vfpcc i8 @return_external() {
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entry:
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%0 = load i8* @external, align 1
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ret i8 %0
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}
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; CHECK-LABEL: return_external
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; CHECK: movw r0, :lower16:external
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; CHECK: movt r0, :upper16:external
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; CHECK: ldrb r0, [r0]
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