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Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.

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No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140470 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-09-25 16:46:08 +00:00
parent fb96574fca
commit 74e2d6ea66
4 changed files with 47 additions and 51 deletions
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7
include/llvm/CodeGen/Passes.h
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@ -132,11 +132,10 @@ namespace llvm {
/// ///
FunctionPass *createPrologEpilogCodeInserter(); FunctionPass *createPrologEpilogCodeInserter();
/// LowerSubregs Pass - This pass lowers subregs to register-register copies /// ExpandPostRAPseudos Pass - This pass expands pseudo instructions after
/// which yields suboptimal, but correct code if the register allocator /// register allocation.
/// cannot coalesce all subreg operations during allocation.
/// ///
FunctionPass *createLowerSubregsPass(); FunctionPass *createExpandPostRAPseudosPass();
/// createPostRAScheduler - This pass performs post register allocation /// createPostRAScheduler - This pass performs post register allocation
/// scheduling. /// scheduling.

83
lib/CodeGen/ExpandPostRAPseudos.cpp
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@ -1,4 +1,4 @@
//===-- LowerSubregs.cpp - Subregister Lowering instruction pass ----------===// //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -7,14 +7,12 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file defines a MachineFunction pass which runs after register // This file defines a pass that expands COPY and SUBREG_TO_REG pseudo
// allocation that turns subreg insert/extract instructions into register // instructions after register allocation.
// copies, as needed. This ensures correct codegen even if the coalescer
// isn't able to remove all subreg instructions.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#define DEBUG_TYPE "lowersubregs" #define DEBUG_TYPE "postrapseudos"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
@ -29,52 +27,51 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
struct LowerSubregsInstructionPass : public MachineFunctionPass { struct ExpandPostRA : public MachineFunctionPass {
private: private:
const TargetRegisterInfo *TRI; const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII; const TargetInstrInfo *TII;
public: public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
LowerSubregsInstructionPass() : MachineFunctionPass(ID) {} ExpandPostRA() : MachineFunctionPass(ID) {}
const char *getPassName() const { const char *getPassName() const {
return "Subregister lowering instruction pass"; return "Post-RA pseudo instruction expansion pass";
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG(); AU.setPreservesCFG();
AU.addPreservedID(MachineLoopInfoID); AU.addPreservedID(MachineLoopInfoID);
AU.addPreservedID(MachineDominatorsID); AU.addPreservedID(MachineDominatorsID);
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
/// runOnMachineFunction - pass entry point /// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&); bool runOnMachineFunction(MachineFunction&);
private: private:
bool LowerSubregToReg(MachineInstr *MI); bool LowerSubregToReg(MachineInstr *MI);
bool LowerCopy(MachineInstr *MI); bool LowerCopy(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg, void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo *TRI); const TargetRegisterInfo *TRI);
void TransferImplicitDefs(MachineInstr *MI); void TransferImplicitDefs(MachineInstr *MI);
}; };
} // end anonymous namespace
char LowerSubregsInstructionPass::ID = 0; char ExpandPostRA::ID = 0;
}
FunctionPass *llvm::createLowerSubregsPass() { FunctionPass *llvm::createExpandPostRAPseudosPass() {
return new LowerSubregsInstructionPass(); return new ExpandPostRA();
} }
/// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead, /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead,
/// and the lowered replacement instructions immediately precede it. /// and the lowered replacement instructions immediately precede it.
/// Mark the replacement instructions with the dead flag. /// Mark the replacement instructions with the dead flag.
void void
LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI, ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
unsigned DstReg, const TargetRegisterInfo *TRI) {
const TargetRegisterInfo *TRI) {
for (MachineBasicBlock::iterator MII = for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) { prior(MachineBasicBlock::iterator(MI)); ; --MII) {
if (MII->addRegisterDead(DstReg, TRI)) if (MII->addRegisterDead(DstReg, TRI))
@ -88,7 +85,7 @@ LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
/// replacement instructions immediately precede it. Copy any implicit-def /// replacement instructions immediately precede it. Copy any implicit-def
/// operands from MI to the replacement instruction. /// operands from MI to the replacement instruction.
void void
LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) { ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) {
MachineBasicBlock::iterator CopyMI = MI; MachineBasicBlock::iterator CopyMI = MI;
--CopyMI; --CopyMI;
@ -100,7 +97,7 @@ LowerSubregsInstructionPass::TransferImplicitDefs(MachineInstr *MI) {
} }
} }
bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
MI->getOperand(1).isImm() && MI->getOperand(1).isImm() &&
@ -152,7 +149,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
return true; return true;
} }
bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) { bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
MachineOperand &DstMO = MI->getOperand(0); MachineOperand &DstMO = MI->getOperand(0);
MachineOperand &SrcMO = MI->getOperand(1); MachineOperand &SrcMO = MI->getOperand(1);
@ -191,9 +188,9 @@ bool LowerSubregsInstructionPass::LowerCopy(MachineInstr *MI) {
/// runOnMachineFunction - Reduce subregister inserts and extracts to register /// runOnMachineFunction - Reduce subregister inserts and extracts to register
/// copies. /// copies.
/// ///
bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) { bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Machine Function\n" DEBUG(dbgs() << "Machine Function\n"
<< "********** LOWERING SUBREG INSTRS **********\n" << "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
<< "********** Function: " << "********** Function: "
<< MF.getFunction()->getName() << '\n'); << MF.getFunction()->getName() << '\n');
TRI = MF.getTarget().getRegisterInfo(); TRI = MF.getTarget().getRegisterInfo();

4
lib/CodeGen/LLVMTargetMachine.cpp
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@ -444,8 +444,8 @@ bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (addPostRegAlloc(PM, OptLevel)) if (addPostRegAlloc(PM, OptLevel))
printAndVerify(PM, "After PostRegAlloc passes"); printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createLowerSubregsPass()); PM.add(createExpandPostRAPseudosPass());
printAndVerify(PM, "After LowerSubregs"); printAndVerify(PM, "After ExpandPostRAPseudos");
// Insert prolog/epilog code. Eliminate abstract frame index references... // Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter()); PM.add(createPrologEpilogCodeInserter());

4
lib/Target/PTX/PTXTargetMachine.cpp
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@ -323,8 +323,8 @@ bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
if (addPostRegAlloc(PM, OptLevel)) if (addPostRegAlloc(PM, OptLevel))
printAndVerify(PM, "After PostRegAlloc passes"); printAndVerify(PM, "After PostRegAlloc passes");
PM.add(createLowerSubregsPass()); PM.add(createExpandPostRAPseudosPass());
printAndVerify(PM, "After LowerSubregs"); printAndVerify(PM, "After ExpandPostRAPseudos");
// Insert prolog/epilog code. Eliminate abstract frame index references... // Insert prolog/epilog code. Eliminate abstract frame index references...
PM.add(createPrologEpilogCodeInserter()); PM.add(createPrologEpilogCodeInserter());