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Still more vector_shuffle pattern removal.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150365 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-02-13 07:23:41 +00:00
parent b83a67e1e3
commit 7505626acd
2 changed files with 9 additions and 39 deletions
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10
lib/Target/X86/X86InstrFragmentsSIMD.td
View File

@ -385,16 +385,6 @@ def movl : PatFrag<(ops node:$lhs, node:$rhs),
return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N)); return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
}]>; }]>;
def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
}]>;
def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
(vector_shuffle node:$lhs, node:$rhs), [{
return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N), Subtarget->hasAVX2());
}]>;
def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index), def vextractf128_extract : PatFrag<(ops node:$bigvec, node:$index),
(extract_subvector node:$bigvec, (extract_subvector node:$bigvec,
node:$index), [{ node:$index), [{

38
lib/Target/X86/X86InstrSSE.td
View File

@ -1192,24 +1192,24 @@ let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst|$dst, $src}", "movhps\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract [(store (f64 (vector_extract
(unpckh (bc_v2f64 (v4f32 VR128:$src)), (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(undef)), (iPTR 0))), addr:$dst)]>, (bc_v2f64 (v4f32 VR128:$src))),
VEX; (iPTR 0))), addr:$dst)]>, VEX;
def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst|$dst, $src}", "movhpd\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract [(store (f64 (vector_extract
(v2f64 (unpckh VR128:$src, (undef))), (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
(iPTR 0))), addr:$dst)]>, (iPTR 0))), addr:$dst)]>, VEX;
VEX;
def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhps\t{$src, $dst|$dst, $src}", "movhps\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract [(store (f64 (vector_extract
(unpckh (bc_v2f64 (v4f32 VR128:$src)), (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(undef)), (iPTR 0))), addr:$dst)]>; (bc_v2f64 (v4f32 VR128:$src))),
(iPTR 0))), addr:$dst)]>;
def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src), def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
"movhpd\t{$src, $dst|$dst, $src}", "movhpd\t{$src, $dst|$dst, $src}",
[(store (f64 (vector_extract [(store (f64 (vector_extract
(v2f64 (unpckh VR128:$src, (undef))), (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
(iPTR 0))), addr:$dst)]>; (iPTR 0))), addr:$dst)]>;
let Predicates = [HasAVX] in { let Predicates = [HasAVX] in {
@ -1238,15 +1238,6 @@ let Predicates = [HasAVX] in {
def : Pat<(v2f64 (X86Movlhpd VR128:$src1, def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))), (scalar_to_vector (loadf64 addr:$src2)))),
(VMOVHPDrm VR128:$src1, addr:$src2)>; (VMOVHPDrm VR128:$src1, addr:$src2)>;
// Store patterns
def : Pat<(store (f64 (vector_extract
(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
(VMOVHPSmr addr:$dst, VR128:$src)>;
def : Pat<(store (f64 (vector_extract
(v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))), addr:$dst),
(VMOVHPDmr addr:$dst, VR128:$src)>;
} }
let Predicates = [HasSSE1] in { let Predicates = [HasSSE1] in {
@ -1262,12 +1253,6 @@ let Predicates = [HasSSE1] in {
def : Pat<(X86Movlhps VR128:$src1, def : Pat<(X86Movlhps VR128:$src1,
(bc_v4f32 (v2i64 (X86vzload addr:$src2)))), (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
(MOVHPSrm VR128:$src1, addr:$src2)>; (MOVHPSrm VR128:$src1, addr:$src2)>;
// Store patterns
def : Pat<(store (f64 (vector_extract
(X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
(bc_v2f64 (v4f32 VR128:$src))), (iPTR 0))), addr:$dst),
(MOVHPSmr addr:$dst, VR128:$src)>;
} }
let Predicates = [HasSSE2] in { let Predicates = [HasSSE2] in {
@ -1283,11 +1268,6 @@ let Predicates = [HasSSE2] in {
def : Pat<(v2f64 (X86Movlhpd VR128:$src1, def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
(scalar_to_vector (loadf64 addr:$src2)))), (scalar_to_vector (loadf64 addr:$src2)))),
(MOVHPDrm VR128:$src1, addr:$src2)>; (MOVHPDrm VR128:$src1, addr:$src2)>;
// Store patterns
def : Pat<(store (f64 (vector_extract
(v2f64 (X86Unpckh VR128:$src, VR128:$src)), (iPTR 0))),addr:$dst),
(MOVHPDmr addr:$dst, VR128:$src)>;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//