6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-06-17 03:29:52 +00:00
Code Issues Projects Releases Wiki Activity

[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239161 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-06-05 16:00:11 +00:00
parent a8769fd4b2
commit 750b351b76
26 changed files with 2865 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

742
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
View File

@ -56,37 +56,43 @@ public:
}
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder);
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, const void *Decoder);
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t Address, void const *Decoder);
uint64_t Address,
void const *Decoder);
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
raw_ostream &os);
static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst);
static const uint16_t IntRegDecoderTable[] = {
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
Hexagon::R30, Hexagon::R31 };
Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,
Hexagon::R30, Hexagon::R31};
static const uint16_t PredRegDecoderTable[] = { Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3 };
static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,
Hexagon::P2, Hexagon::P3};
static DecodeStatus DecodeRegisterClass(MCInst &Inst, unsigned RegNo,
const uint16_t Table[], size_t Size) {
const uint16_t Table[], size_t Size) {
if (RegNo < Size) {
Inst.addOperand(MCOperand::createReg(Table[RegNo]));
return MCDisassembler::Success;
}
else
} else
return MCDisassembler::Fail;
}
static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
void const *Decoder) {
uint64_t /*Address*/,
void const *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
@ -96,13 +102,13 @@ static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, const void *Decoder) {
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t CtrlRegDecoderTable[] = {
Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH
};
Hexagon::SA0, Hexagon::LC0, Hexagon::SA1, Hexagon::LC1,
Hexagon::P3_0, Hexagon::NoRegister, Hexagon::C6, Hexagon::C7,
Hexagon::USR, Hexagon::PC, Hexagon::UGP, Hexagon::GP,
Hexagon::CS0, Hexagon::CS1, Hexagon::UPCL, Hexagon::UPCH};
if (RegNo >= sizeof(CtrlRegDecoderTable) / sizeof(CtrlRegDecoderTable[0]))
return MCDisassembler::Fail;
@ -116,17 +122,15 @@ static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, void const *Decoder) {
uint64_t /*Address*/,
void const *Decoder) {
static const uint16_t CtrlReg64DecoderTable[] = {
Hexagon::C1_0, Hexagon::NoRegister,
Hexagon::C3_2, Hexagon::NoRegister,
Hexagon::NoRegister, Hexagon::NoRegister,
Hexagon::C7_6, Hexagon::NoRegister,
Hexagon::C9_8, Hexagon::NoRegister,
Hexagon::C11_10, Hexagon::NoRegister,
Hexagon::CS, Hexagon::NoRegister,
Hexagon::UPC, Hexagon::NoRegister
};
Hexagon::C1_0, Hexagon::NoRegister, Hexagon::C3_2,
Hexagon::NoRegister, Hexagon::NoRegister, Hexagon::NoRegister,
Hexagon::C7_6, Hexagon::NoRegister, Hexagon::C9_8,
Hexagon::NoRegister, Hexagon::C11_10, Hexagon::NoRegister,
Hexagon::CS, Hexagon::NoRegister, Hexagon::UPC,
Hexagon::NoRegister};
if (RegNo >= sizeof(CtrlReg64DecoderTable) / sizeof(CtrlReg64DecoderTable[0]))
return MCDisassembler::Fail;
@ -140,7 +144,8 @@ static DecodeStatus DecodeCtrRegs64RegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, const void *Decoder) {
uint64_t /*Address*/,
const void *Decoder) {
unsigned Register = 0;
switch (RegNo) {
case 0:
@ -157,22 +162,21 @@ static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo,
}
static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/, const void *Decoder) {
uint64_t /*Address*/,
const void *Decoder) {
static const uint16_t DoubleRegDecoderTable[] = {
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15
};
Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
Hexagon::D4, Hexagon::D5, Hexagon::D6, Hexagon::D7,
Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
Hexagon::D12, Hexagon::D13, Hexagon::D14, Hexagon::D15};
return (DecodeRegisterClass(Inst, RegNo >> 1,
DoubleRegDecoderTable,
sizeof (DoubleRegDecoderTable)));
return (DecodeRegisterClass(Inst, RegNo >> 1, DoubleRegDecoderTable,
sizeof(DoubleRegDecoderTable)));
}
static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
uint64_t /*Address*/,
void const *Decoder) {
uint64_t /*Address*/,
void const *Decoder) {
if (RegNo > 3)
return MCDisassembler::Fail;
@ -206,11 +210,10 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
*CurrentBundle = &MI;
MI.setOpcode(Hexagon::BUNDLE);
MI.addOperand(MCOperand::createImm(0));
while (Result == Success && Complete == false)
{
while (Result == Success && Complete == false) {
if (Bytes.size() < HEXAGON_INSTR_SIZE)
return MCDisassembler::Fail;
MCInst * Inst = new (getContext()) MCInst;
MCInst *Inst = new (getContext()) MCInst;
Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
MI.addOperand(MCOperand::createInst(Inst));
Size += HEXAGON_INSTR_SIZE;
@ -241,11 +244,646 @@ DecodeStatus HexagonDisassembler::getSingleInstruction(
DecodeStatus Result = DecodeStatus::Success;
if ((Instruction & HexagonII::INST_PARSE_MASK) ==
HexagonII::INST_PARSE_PACKET_END)
HexagonII::INST_PARSE_DUPLEX) {
// Determine the instruction class of each instruction in the duplex.
unsigned duplexIClass, IClassLow, IClassHigh;
duplexIClass = ((Instruction >> 28) & 0xe) | ((Instruction >> 13) & 0x1);
switch (duplexIClass) {
default:
return MCDisassembler::Fail;
case 0:
IClassLow = HexagonII::HSIG_L1;
IClassHigh = HexagonII::HSIG_L1;
break;
case 1:
IClassLow = HexagonII::HSIG_L2;
IClassHigh = HexagonII::HSIG_L1;
break;
case 2:
IClassLow = HexagonII::HSIG_L2;
IClassHigh = HexagonII::HSIG_L2;
break;
case 3:
IClassLow = HexagonII::HSIG_A;
IClassHigh = HexagonII::HSIG_A;
break;
case 4:
IClassLow = HexagonII::HSIG_L1;
IClassHigh = HexagonII::HSIG_A;
break;
case 5:
IClassLow = HexagonII::HSIG_L2;
IClassHigh = HexagonII::HSIG_A;
break;
case 6:
IClassLow = HexagonII::HSIG_S1;
IClassHigh = HexagonII::HSIG_A;
break;
case 7:
IClassLow = HexagonII::HSIG_S2;
IClassHigh = HexagonII::HSIG_A;
break;
case 8:
IClassLow = HexagonII::HSIG_S1;
IClassHigh = HexagonII::HSIG_L1;
break;
case 9:
IClassLow = HexagonII::HSIG_S1;
IClassHigh = HexagonII::HSIG_L2;
break;
case 10:
IClassLow = HexagonII::HSIG_S1;
IClassHigh = HexagonII::HSIG_S1;
break;
case 11:
IClassLow = HexagonII::HSIG_S2;
IClassHigh = HexagonII::HSIG_S1;
break;
case 12:
IClassLow = HexagonII::HSIG_S2;
IClassHigh = HexagonII::HSIG_L1;
break;
case 13:
IClassLow = HexagonII::HSIG_S2;
IClassHigh = HexagonII::HSIG_L2;
break;
case 14:
IClassLow = HexagonII::HSIG_S2;
IClassHigh = HexagonII::HSIG_S2;
break;
}
// Set the MCInst to be a duplex instruction. Which one doesn't matter.
MI.setOpcode(Hexagon::DuplexIClass0);
// Decode each instruction in the duplex.
// Create an MCInst for each instruction.
unsigned instLow = Instruction & 0x1fff;
unsigned instHigh = (Instruction >> 16) & 0x1fff;
unsigned opLow;
if (GetSubinstOpcode(IClassLow, instLow, opLow, os) !=
MCDisassembler::Success)
return MCDisassembler::Fail;
unsigned opHigh;
if (GetSubinstOpcode(IClassHigh, instHigh, opHigh, os) !=
MCDisassembler::Success)
return MCDisassembler::Fail;
MCInst *MILow = new (getContext()) MCInst;
MILow->setOpcode(opLow);
MCInst *MIHigh = new (getContext()) MCInst;
MIHigh->setOpcode(opHigh);
AddSubinstOperands(MILow, opLow, instLow);
AddSubinstOperands(MIHigh, opHigh, instHigh);
// see ConvertToSubInst() in
// lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp
// Add the duplex instruction MCInsts as operands to the passed in MCInst.
MCOperand OPLow = MCOperand::createInst(MILow);
MCOperand OPHigh = MCOperand::createInst(MIHigh);
MI.addOperand(OPLow);
MI.addOperand(OPHigh);
Complete = true;
// Calling the auto-generated decoder function.
Result =
decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
} else {
if ((Instruction & HexagonII::INST_PARSE_MASK) ==
HexagonII::INST_PARSE_PACKET_END)
Complete = true;
// Calling the auto-generated decoder function.
Result =
decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
}
return Result;
}
// These values are from HexagonGenMCCodeEmitter.inc and HexagonIsetDx.td
enum subInstBinaryValues {
V4_SA1_addi_BITS = 0x0000,
V4_SA1_addi_MASK = 0x1800,
V4_SA1_addrx_BITS = 0x1800,
V4_SA1_addrx_MASK = 0x1f00,
V4_SA1_addsp_BITS = 0x0c00,
V4_SA1_addsp_MASK = 0x1c00,
V4_SA1_and1_BITS = 0x1200,
V4_SA1_and1_MASK = 0x1f00,
V4_SA1_clrf_BITS = 0x1a70,
V4_SA1_clrf_MASK = 0x1e70,
V4_SA1_clrfnew_BITS = 0x1a50,
V4_SA1_clrfnew_MASK = 0x1e70,
V4_SA1_clrt_BITS = 0x1a60,
V4_SA1_clrt_MASK = 0x1e70,
V4_SA1_clrtnew_BITS = 0x1a40,
V4_SA1_clrtnew_MASK = 0x1e70,
V4_SA1_cmpeqi_BITS = 0x1900,
V4_SA1_cmpeqi_MASK = 0x1f00,
V4_SA1_combine0i_BITS = 0x1c00,
V4_SA1_combine0i_MASK = 0x1d18,
V4_SA1_combine1i_BITS = 0x1c08,
V4_SA1_combine1i_MASK = 0x1d18,
V4_SA1_combine2i_BITS = 0x1c10,
V4_SA1_combine2i_MASK = 0x1d18,
V4_SA1_combine3i_BITS = 0x1c18,
V4_SA1_combine3i_MASK = 0x1d18,
V4_SA1_combinerz_BITS = 0x1d08,
V4_SA1_combinerz_MASK = 0x1d08,
V4_SA1_combinezr_BITS = 0x1d00,
V4_SA1_combinezr_MASK = 0x1d08,
V4_SA1_dec_BITS = 0x1300,
V4_SA1_dec_MASK = 0x1f00,
V4_SA1_inc_BITS = 0x1100,
V4_SA1_inc_MASK = 0x1f00,
V4_SA1_seti_BITS = 0x0800,
V4_SA1_seti_MASK = 0x1c00,
V4_SA1_setin1_BITS = 0x1a00,
V4_SA1_setin1_MASK = 0x1e40,
V4_SA1_sxtb_BITS = 0x1500,
V4_SA1_sxtb_MASK = 0x1f00,
V4_SA1_sxth_BITS = 0x1400,
V4_SA1_sxth_MASK = 0x1f00,
V4_SA1_tfr_BITS = 0x1000,
V4_SA1_tfr_MASK = 0x1f00,
V4_SA1_zxtb_BITS = 0x1700,
V4_SA1_zxtb_MASK = 0x1f00,
V4_SA1_zxth_BITS = 0x1600,
V4_SA1_zxth_MASK = 0x1f00,
V4_SL1_loadri_io_BITS = 0x0000,
V4_SL1_loadri_io_MASK = 0x1000,
V4_SL1_loadrub_io_BITS = 0x1000,
V4_SL1_loadrub_io_MASK = 0x1000,
V4_SL2_deallocframe_BITS = 0x1f00,
V4_SL2_deallocframe_MASK = 0x1fc0,
V4_SL2_jumpr31_BITS = 0x1fc0,
V4_SL2_jumpr31_MASK = 0x1fc4,
V4_SL2_jumpr31_f_BITS = 0x1fc5,
V4_SL2_jumpr31_f_MASK = 0x1fc7,
V4_SL2_jumpr31_fnew_BITS = 0x1fc7,
V4_SL2_jumpr31_fnew_MASK = 0x1fc7,
V4_SL2_jumpr31_t_BITS = 0x1fc4,
V4_SL2_jumpr31_t_MASK = 0x1fc7,
V4_SL2_jumpr31_tnew_BITS = 0x1fc6,
V4_SL2_jumpr31_tnew_MASK = 0x1fc7,
V4_SL2_loadrb_io_BITS = 0x1000,
V4_SL2_loadrb_io_MASK = 0x1800,
V4_SL2_loadrd_sp_BITS = 0x1e00,
V4_SL2_loadrd_sp_MASK = 0x1f00,
V4_SL2_loadrh_io_BITS = 0x0000,
V4_SL2_loadrh_io_MASK = 0x1800,
V4_SL2_loadri_sp_BITS = 0x1c00,
V4_SL2_loadri_sp_MASK = 0x1e00,
V4_SL2_loadruh_io_BITS = 0x0800,
V4_SL2_loadruh_io_MASK = 0x1800,
V4_SL2_return_BITS = 0x1f40,
V4_SL2_return_MASK = 0x1fc4,
V4_SL2_return_f_BITS = 0x1f45,
V4_SL2_return_f_MASK = 0x1fc7,
V4_SL2_return_fnew_BITS = 0x1f47,
V4_SL2_return_fnew_MASK = 0x1fc7,
V4_SL2_return_t_BITS = 0x1f44,
V4_SL2_return_t_MASK = 0x1fc7,
V4_SL2_return_tnew_BITS = 0x1f46,
V4_SL2_return_tnew_MASK = 0x1fc7,
V4_SS1_storeb_io_BITS = 0x1000,
V4_SS1_storeb_io_MASK = 0x1000,
V4_SS1_storew_io_BITS = 0x0000,
V4_SS1_storew_io_MASK = 0x1000,
V4_SS2_allocframe_BITS = 0x1c00,
V4_SS2_allocframe_MASK = 0x1e00,
V4_SS2_storebi0_BITS = 0x1200,
V4_SS2_storebi0_MASK = 0x1f00,
V4_SS2_storebi1_BITS = 0x1300,
V4_SS2_storebi1_MASK = 0x1f00,
V4_SS2_stored_sp_BITS = 0x0a00,
V4_SS2_stored_sp_MASK = 0x1e00,
V4_SS2_storeh_io_BITS = 0x0000,
V4_SS2_storeh_io_MASK = 0x1800,
V4_SS2_storew_sp_BITS = 0x0800,
V4_SS2_storew_sp_MASK = 0x1e00,
V4_SS2_storewi0_BITS = 0x1000,
V4_SS2_storewi0_MASK = 0x1f00,
V4_SS2_storewi1_BITS = 0x1100,
V4_SS2_storewi1_MASK = 0x1f00
};
static unsigned GetSubinstOpcode(unsigned IClass, unsigned inst, unsigned &op,
raw_ostream &os) {
switch (IClass) {
case HexagonII::HSIG_L1:
if ((inst & V4_SL1_loadri_io_MASK) == V4_SL1_loadri_io_BITS)
op = Hexagon::V4_SL1_loadri_io;
else if ((inst & V4_SL1_loadrub_io_MASK) == V4_SL1_loadrub_io_BITS)
op = Hexagon::V4_SL1_loadrub_io;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_L2:
if ((inst & V4_SL2_deallocframe_MASK) == V4_SL2_deallocframe_BITS)
op = Hexagon::V4_SL2_deallocframe;
else if ((inst & V4_SL2_jumpr31_MASK) == V4_SL2_jumpr31_BITS)
op = Hexagon::V4_SL2_jumpr31;
else if ((inst & V4_SL2_jumpr31_f_MASK) == V4_SL2_jumpr31_f_BITS)
op = Hexagon::V4_SL2_jumpr31_f;
else if ((inst & V4_SL2_jumpr31_fnew_MASK) == V4_SL2_jumpr31_fnew_BITS)
op = Hexagon::V4_SL2_jumpr31_fnew;
else if ((inst & V4_SL2_jumpr31_t_MASK) == V4_SL2_jumpr31_t_BITS)
op = Hexagon::V4_SL2_jumpr31_t;
else if ((inst & V4_SL2_jumpr31_tnew_MASK) == V4_SL2_jumpr31_tnew_BITS)
op = Hexagon::V4_SL2_jumpr31_tnew;
else if ((inst & V4_SL2_loadrb_io_MASK) == V4_SL2_loadrb_io_BITS)
op = Hexagon::V4_SL2_loadrb_io;
else if ((inst & V4_SL2_loadrd_sp_MASK) == V4_SL2_loadrd_sp_BITS)
op = Hexagon::V4_SL2_loadrd_sp;
else if ((inst & V4_SL2_loadrh_io_MASK) == V4_SL2_loadrh_io_BITS)
op = Hexagon::V4_SL2_loadrh_io;
else if ((inst & V4_SL2_loadri_sp_MASK) == V4_SL2_loadri_sp_BITS)
op = Hexagon::V4_SL2_loadri_sp;
else if ((inst & V4_SL2_loadruh_io_MASK) == V4_SL2_loadruh_io_BITS)
op = Hexagon::V4_SL2_loadruh_io;
else if ((inst & V4_SL2_return_MASK) == V4_SL2_return_BITS)
op = Hexagon::V4_SL2_return;
else if ((inst & V4_SL2_return_f_MASK) == V4_SL2_return_f_BITS)
op = Hexagon::V4_SL2_return_f;
else if ((inst & V4_SL2_return_fnew_MASK) == V4_SL2_return_fnew_BITS)
op = Hexagon::V4_SL2_return_fnew;
else if ((inst & V4_SL2_return_t_MASK) == V4_SL2_return_t_BITS)
op = Hexagon::V4_SL2_return_t;
else if ((inst & V4_SL2_return_tnew_MASK) == V4_SL2_return_tnew_BITS)
op = Hexagon::V4_SL2_return_tnew;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_A:
if ((inst & V4_SA1_addi_MASK) == V4_SA1_addi_BITS)
op = Hexagon::V4_SA1_addi;
else if ((inst & V4_SA1_addrx_MASK) == V4_SA1_addrx_BITS)
op = Hexagon::V4_SA1_addrx;
else if ((inst & V4_SA1_addsp_MASK) == V4_SA1_addsp_BITS)
op = Hexagon::V4_SA1_addsp;
else if ((inst & V4_SA1_and1_MASK) == V4_SA1_and1_BITS)
op = Hexagon::V4_SA1_and1;
else if ((inst & V4_SA1_clrf_MASK) == V4_SA1_clrf_BITS)
op = Hexagon::V4_SA1_clrf;
else if ((inst & V4_SA1_clrfnew_MASK) == V4_SA1_clrfnew_BITS)
op = Hexagon::V4_SA1_clrfnew;
else if ((inst & V4_SA1_clrt_MASK) == V4_SA1_clrt_BITS)
op = Hexagon::V4_SA1_clrt;
else if ((inst & V4_SA1_clrtnew_MASK) == V4_SA1_clrtnew_BITS)
op = Hexagon::V4_SA1_clrtnew;
else if ((inst & V4_SA1_cmpeqi_MASK) == V4_SA1_cmpeqi_BITS)
op = Hexagon::V4_SA1_cmpeqi;
else if ((inst & V4_SA1_combine0i_MASK) == V4_SA1_combine0i_BITS)
op = Hexagon::V4_SA1_combine0i;
else if ((inst & V4_SA1_combine1i_MASK) == V4_SA1_combine1i_BITS)
op = Hexagon::V4_SA1_combine1i;
else if ((inst & V4_SA1_combine2i_MASK) == V4_SA1_combine2i_BITS)
op = Hexagon::V4_SA1_combine2i;
else if ((inst & V4_SA1_combine3i_MASK) == V4_SA1_combine3i_BITS)
op = Hexagon::V4_SA1_combine3i;
else if ((inst & V4_SA1_combinerz_MASK) == V4_SA1_combinerz_BITS)
op = Hexagon::V4_SA1_combinerz;
else if ((inst & V4_SA1_combinezr_MASK) == V4_SA1_combinezr_BITS)
op = Hexagon::V4_SA1_combinezr;
else if ((inst & V4_SA1_dec_MASK) == V4_SA1_dec_BITS)
op = Hexagon::V4_SA1_dec;
else if ((inst & V4_SA1_inc_MASK) == V4_SA1_inc_BITS)
op = Hexagon::V4_SA1_inc;
else if ((inst & V4_SA1_seti_MASK) == V4_SA1_seti_BITS)
op = Hexagon::V4_SA1_seti;
else if ((inst & V4_SA1_setin1_MASK) == V4_SA1_setin1_BITS)
op = Hexagon::V4_SA1_setin1;
else if ((inst & V4_SA1_sxtb_MASK) == V4_SA1_sxtb_BITS)
op = Hexagon::V4_SA1_sxtb;
else if ((inst & V4_SA1_sxth_MASK) == V4_SA1_sxth_BITS)
op = Hexagon::V4_SA1_sxth;
else if ((inst & V4_SA1_tfr_MASK) == V4_SA1_tfr_BITS)
op = Hexagon::V4_SA1_tfr;
else if ((inst & V4_SA1_zxtb_MASK) == V4_SA1_zxtb_BITS)
op = Hexagon::V4_SA1_zxtb;
else if ((inst & V4_SA1_zxth_MASK) == V4_SA1_zxth_BITS)
op = Hexagon::V4_SA1_zxth;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_S1:
if ((inst & V4_SS1_storeb_io_MASK) == V4_SS1_storeb_io_BITS)
op = Hexagon::V4_SS1_storeb_io;
else if ((inst & V4_SS1_storew_io_MASK) == V4_SS1_storew_io_BITS)
op = Hexagon::V4_SS1_storew_io;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
case HexagonII::HSIG_S2:
if ((inst & V4_SS2_allocframe_MASK) == V4_SS2_allocframe_BITS)
op = Hexagon::V4_SS2_allocframe;
else if ((inst & V4_SS2_storebi0_MASK) == V4_SS2_storebi0_BITS)
op = Hexagon::V4_SS2_storebi0;
else if ((inst & V4_SS2_storebi1_MASK) == V4_SS2_storebi1_BITS)
op = Hexagon::V4_SS2_storebi1;
else if ((inst & V4_SS2_stored_sp_MASK) == V4_SS2_stored_sp_BITS)
op = Hexagon::V4_SS2_stored_sp;
else if ((inst & V4_SS2_storeh_io_MASK) == V4_SS2_storeh_io_BITS)
op = Hexagon::V4_SS2_storeh_io;
else if ((inst & V4_SS2_storew_sp_MASK) == V4_SS2_storew_sp_BITS)
op = Hexagon::V4_SS2_storew_sp;
else if ((inst & V4_SS2_storewi0_MASK) == V4_SS2_storewi0_BITS)
op = Hexagon::V4_SS2_storewi0;
else if ((inst & V4_SS2_storewi1_MASK) == V4_SS2_storewi1_BITS)
op = Hexagon::V4_SS2_storewi1;
else {
os << "<unknown subinstruction>";
return MCDisassembler::Fail;
}
break;
default:
os << "<unknown>";
return MCDisassembler::Fail;
}
return MCDisassembler::Success;
}
static unsigned getRegFromSubinstEncoding(unsigned encoded_reg) {
if (encoded_reg < 8)
return Hexagon::R0 + encoded_reg;
else if (encoded_reg < 16)
return Hexagon::R0 + encoded_reg + 8;
return Hexagon::NoRegister;
}
static unsigned getDRegFromSubinstEncoding(unsigned encoded_dreg) {
if (encoded_dreg < 4)
return Hexagon::D0 + encoded_dreg;
else if (encoded_dreg < 8)
return Hexagon::D0 + encoded_dreg + 4;
return Hexagon::NoRegister;
}
static void AddSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) {
int64_t operand;
MCOperand Op;
switch (opcode) {
case Hexagon::V4_SL2_deallocframe:
case Hexagon::V4_SL2_jumpr31:
case Hexagon::V4_SL2_jumpr31_f:
case Hexagon::V4_SL2_jumpr31_fnew:
case Hexagon::V4_SL2_jumpr31_t:
case Hexagon::V4_SL2_jumpr31_tnew:
case Hexagon::V4_SL2_return:
case Hexagon::V4_SL2_return_f:
case Hexagon::V4_SL2_return_fnew:
case Hexagon::V4_SL2_return_t:
case Hexagon::V4_SL2_return_tnew:
// no operands for these instructions
break;
case Hexagon::V4_SS2_allocframe:
// u 8-4{5_3}
operand = ((inst & 0x1f0) >> 4) << 3;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL1_loadri_io:
// Rd 3-0, Rs 7-4, u 11-8{4_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0xf00) >> 6;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL1_loadrub_io:
// Rd 3-0, Rs 7-4, u 11-8
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0xf00) >> 8;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL2_loadrb_io:
// Rd 3-0, Rs 7-4, u 10-8
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0x700) >> 8;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL2_loadrh_io:
case Hexagon::V4_SL2_loadruh_io:
// Rd 3-0, Rs 7-4, u 10-8{3_1}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0x700) >> 8) << 1;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL2_loadrd_sp:
// Rdd 2-0, u 7-3{5_3}
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0x0f8) >> 3) << 3;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SL2_loadri_sp:
// Rd 3-0, u 8-4{5_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0x1f0) >> 4) << 2;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_addi:
// Rx 3-0 (x2), s7 10-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
MI->addOperand(Op);
operand = SignExtend64<7>((inst & 0x7f0) >> 4);
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_addrx:
// Rx 3-0 (x2), Rs 7-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
case Hexagon::V4_SA1_and1:
case Hexagon::V4_SA1_dec:
case Hexagon::V4_SA1_inc:
case Hexagon::V4_SA1_sxtb:
case Hexagon::V4_SA1_sxth:
case Hexagon::V4_SA1_tfr:
case Hexagon::V4_SA1_zxtb:
case Hexagon::V4_SA1_zxth:
// Rd 3-0, Rs 7-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_addsp:
// Rd 3-0, u 9-4{6_2}
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0x3f0) >> 4) << 2;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_seti:
// Rd 3-0, u 9-4
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0x3f0) >> 4;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_clrf:
case Hexagon::V4_SA1_clrfnew:
case Hexagon::V4_SA1_clrt:
case Hexagon::V4_SA1_clrtnew:
case Hexagon::V4_SA1_setin1:
// Rd 3-0
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_cmpeqi:
// Rs 7-4, u 1-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = inst & 0x3;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_combine0i:
case Hexagon::V4_SA1_combine1i:
case Hexagon::V4_SA1_combine2i:
case Hexagon::V4_SA1_combine3i:
// Rdd 2-0, u 6-5
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0x060) >> 5;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SA1_combinerz:
case Hexagon::V4_SA1_combinezr:
// Rdd 2-0, Rs 7-4
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS1_storeb_io:
// Rs 7-4, u 11-8, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0xf00) >> 8;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS1_storew_io:
// Rs 7-4, u 11-8{4_2}, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0xf00) >> 8) << 2;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS2_storebi0:
case Hexagon::V4_SS2_storebi1:
// Rs 7-4, u 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = inst & 0xf;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS2_storewi0:
case Hexagon::V4_SS2_storewi1:
// Rs 7-4, u 3-0{4_2}
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = (inst & 0xf) << 2;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS2_stored_sp:
// s 8-3{6_3}, Rtt 2-0
operand = SignExtend64<9>(((inst & 0x1f8) >> 3) << 3);
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
operand = getDRegFromSubinstEncoding(inst & 0x7);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
case Hexagon::V4_SS2_storeh_io:
// Rs 7-4, u 10-8{3_1}, Rt 3-0
operand = getRegFromSubinstEncoding((inst & 0xf0) >> 4);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
operand = ((inst & 0x700) >> 8) << 1;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
case Hexagon::V4_SS2_storew_sp:
// u 8-4{5_2}, Rd 3-0
operand = ((inst & 0x1f0) >> 4) << 2;
Op = MCOperand::createImm(operand);
MI->addOperand(Op);
operand = getRegFromSubinstEncoding(inst & 0xf);
Op = MCOperand::createReg(operand);
MI->addOperand(Op);
break;
default:
// don't crash with an invalid subinstruction
// llvm_unreachable("Invalid subinstruction in duplex instruction");
break;
}
}

8
lib/Target/Hexagon/HexagonAsmPrinter.cpp
View File

@ -20,6 +20,7 @@
#include "HexagonTargetMachine.h"
#include "MCTargetDesc/HexagonInstPrinter.h"
#include "MCTargetDesc/HexagonMCInstrInfo.h"
#include "MCTargetDesc/HexagonMCShuffler.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringExtras.h"
@ -199,9 +200,12 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
HexagonLowerToMC(MI, MCB, *this);
HexagonMCInstrInfo::padEndloop(MCB);
}
// Examine the packet and convert pairs of instructions to duplex
// instructions when possible.
SmallVector<DuplexCandidate, 8> possibleDuplexes;
possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(*Subtarget->getInstrInfo(), MCB);
HexagonMCShuffle(*Subtarget->getInstrInfo(), *Subtarget, OutStreamer->getContext(), MCB, possibleDuplexes);
EmitToStreamer(*OutStreamer, MCB);
return;
}
extern "C" void LLVMInitializeHexagonAsmPrinter() {

5
lib/Target/Hexagon/HexagonInstrFormatsV4.td
View File

@ -146,6 +146,11 @@ class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
: InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
TypePREFIX>, OpcodeHexagon;
class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypeDUPLEX>,
OpcodeHexagon;
class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
string cstr = "">
: InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCOMPOUND>,

4
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -4263,3 +4263,7 @@ def J4_jumpsetr: CJInst <
let Inst{19-16} = Rs;
let Inst{7-1} = r9_2{8-2};
}
// Duplex instructions
//===----------------------------------------------------------------------===//
include "HexagonIsetDx.td"

728
lib/Target/Hexagon/HexagonIsetDx.td Normal file
View File

@ -0,0 +1,728 @@
//=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Hexagon duplex instructions.
//
//===----------------------------------------------------------------------===//
// SA1_combine1i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combine1i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#1, #$u2)"> {
bits<3> Rdd;
bits<2> u2;
let Inst{12-10} = 0b111;
let Inst{8} = 0b0;
let Inst{4-3} = 0b01;
let Inst{2-0} = Rdd;
let Inst{6-5} = u2;
}
// SL2_jumpr31_f: Indirect conditional jump if false.
// SL2_jumpr31_f -> SL2_jumpr31_fnew
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
def V4_SL2_jumpr31_f: SUBInst <
(outs ),
(ins ),
"if (!p0) jumpr r31"> {
let Inst{12-6} = 0b1111111;
let Inst{2-0} = 0b101;
}
// SL2_deallocframe: Deallocate stack frame.
let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
def V4_SL2_deallocframe: SUBInst <
(outs ),
(ins ),
"deallocframe"> {
let Inst{12-6} = 0b1111100;
let Inst{2} = 0b0;
}
// SL2_return_f: Deallocate stack frame and return.
// SL2_return_f -> SL2_return_fnew
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
def V4_SL2_return_f: SUBInst <
(outs ),
(ins ),
"if (!p0) dealloc_return"> {
let Inst{12-6} = 0b1111101;
let Inst{2-0} = 0b101;
}
// SA1_combine3i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combine3i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#3, #$u2)"> {
bits<3> Rdd;
bits<2> u2;
let Inst{12-10} = 0b111;
let Inst{8} = 0b0;
let Inst{4-3} = 0b11;
let Inst{2-0} = Rdd;
let Inst{6-5} = u2;
}
// SS2_storebi0: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
def V4_SS2_storebi0: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"memb($Rs + #$u4_0)=#0"> {
bits<4> Rs;
bits<4> u4_0;
let Inst{12-8} = 0b10010;
let Inst{7-4} = Rs;
let Inst{3-0} = u4_0;
}
// SA1_clrtnew: Clear if true.
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrtnew: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (p0.new) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
let Inst{6-4} = 0b100;
let Inst{3-0} = Rd;
}
// SL2_loadruh_io: Load half.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL2_loadruh_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_1Imm:$u3_1),
"$Rd = memuh($Rs + #$u3_1)"> {
bits<4> Rd;
bits<4> Rs;
bits<4> u3_1;
let Inst{12-11} = 0b01;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
let Inst{10-8} = u3_1{3-1};
}
// SL2_jumpr31_tnew: Indirect conditional jump if true.
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
def V4_SL2_jumpr31_tnew: SUBInst <
(outs ),
(ins ),
"if (p0.new) jumpr:nt r31"> {
let Inst{12-6} = 0b1111111;
let Inst{2-0} = 0b110;
}
// SA1_addi: Add.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in
def V4_SA1_addi: SUBInst <
(outs IntRegs:$Rx),
(ins IntRegs:$_src_, s7Ext:$s7),
"$Rx = add($_src_, #$s7)" ,
[] ,
"$_src_ = $Rx"> {
bits<4> Rx;
bits<7> s7;
let Inst{12-11} = 0b00;
let Inst{3-0} = Rx;
let Inst{10-4} = s7;
}
// SL1_loadrub_io: Load byte.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL1_loadrub_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"$Rd = memub($Rs + #$u4_0)"> {
bits<4> Rd;
bits<4> Rs;
bits<4> u4_0;
let Inst{12} = 0b1;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
let Inst{11-8} = u4_0;
}
// SL1_loadri_io: Load word.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL1_loadri_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"$Rd = memw($Rs + #$u4_2)"> {
bits<4> Rd;
bits<4> Rs;
bits<6> u4_2;
let Inst{12} = 0b0;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
let Inst{11-8} = u4_2{5-2};
}
// SA1_cmpeqi: Compareimmed.
let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_cmpeqi: SUBInst <
(outs ),
(ins IntRegs:$Rs, u2Imm:$u2),
"p0 = cmp.eq($Rs, #$u2)"> {
bits<4> Rs;
bits<2> u2;
let Inst{12-8} = 0b11001;
let Inst{7-4} = Rs;
let Inst{1-0} = u2;
}
// SA1_combinerz: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combinerz: SUBInst <
(outs DoubleRegs:$Rdd),
(ins IntRegs:$Rs),
"$Rdd = combine($Rs, #0)"> {
bits<3> Rdd;
bits<4> Rs;
let Inst{12-10} = 0b111;
let Inst{8} = 0b1;
let Inst{3} = 0b1;
let Inst{2-0} = Rdd;
let Inst{7-4} = Rs;
}
// SL2_return_t: Deallocate stack frame and return.
// SL2_return_t -> SL2_return_tnew
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
def V4_SL2_return_t: SUBInst <
(outs ),
(ins ),
"if (p0) dealloc_return"> {
let Inst{12-6} = 0b1111101;
let Inst{2-0} = 0b100;
}
// SS2_allocframe: Allocate stack frame.
let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
def V4_SS2_allocframe: SUBInst <
(outs ),
(ins u5_3Imm:$u5_3),
"allocframe(#$u5_3)"> {
bits<8> u5_3;
let Inst{12-9} = 0b1110;
let Inst{8-4} = u5_3{7-3};
}
// SS2_storeh_io: Store half.
let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in
def V4_SS2_storeh_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt),
"memh($Rs + #$u3_1) = $Rt"> {
bits<4> Rs;
bits<4> u3_1;
bits<4> Rt;
let Inst{12-11} = 0b00;
let Inst{7-4} = Rs;
let Inst{10-8} = u3_1{3-1};
let Inst{3-0} = Rt;
}
// SS2_storewi0: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
def V4_SS2_storewi0: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"memw($Rs + #$u4_2)=#0"> {
bits<4> Rs;
bits<6> u4_2;
let Inst{12-8} = 0b10000;
let Inst{7-4} = Rs;
let Inst{3-0} = u4_2{5-2};
}
// SS2_storewi1: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
def V4_SS2_storewi1: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2),
"memw($Rs + #$u4_2)=#1"> {
bits<4> Rs;
bits<6> u4_2;
let Inst{12-8} = 0b10001;
let Inst{7-4} = Rs;
let Inst{3-0} = u4_2{5-2};
}
// SL2_jumpr31: Indirect conditional jump if true.
let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
def V4_SL2_jumpr31: SUBInst <
(outs ),
(ins ),
"jumpr r31"> {
let Inst{12-6} = 0b1111111;
let Inst{2} = 0b0;
}
// SA1_combinezr: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combinezr: SUBInst <
(outs DoubleRegs:$Rdd),
(ins IntRegs:$Rs),
"$Rdd = combine(#0, $Rs)"> {
bits<3> Rdd;
bits<4> Rs;
let Inst{12-10} = 0b111;
let Inst{8} = 0b1;
let Inst{3} = 0b0;
let Inst{2-0} = Rdd;
let Inst{7-4} = Rs;
}
// SL2_loadrh_io: Load half.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL2_loadrh_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_1Imm:$u3_1),
"$Rd = memh($Rs + #$u3_1)"> {
bits<4> Rd;
bits<4> Rs;
bits<4> u3_1;
let Inst{12-11} = 0b00;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
let Inst{10-8} = u3_1{3-1};
}
// SA1_addrx: Add.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_addrx: SUBInst <
(outs IntRegs:$Rx),
(ins IntRegs:$_src_, IntRegs:$Rs),
"$Rx = add($_src_, $Rs)" ,
[] ,
"$_src_ = $Rx"> {
bits<4> Rx;
bits<4> Rs;
let Inst{12-8} = 0b11000;
let Inst{3-0} = Rx;
let Inst{7-4} = Rs;
}
// SA1_setin1: Set to -1.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_setin1: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"$Rd = #-1"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
let Inst{6} = 0b0;
let Inst{3-0} = Rd;
}
// SA1_sxth: Sxth.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_sxth: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = sxth($Rs)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10100;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SA1_combine0i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combine0i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#0, #$u2)"> {
bits<3> Rdd;
bits<2> u2;
let Inst{12-10} = 0b111;
let Inst{8} = 0b0;
let Inst{4-3} = 0b00;
let Inst{2-0} = Rdd;
let Inst{6-5} = u2;
}
// SA1_combine2i: Combines.
let isCodeGenOnly = 1, hasSideEffects = 0 in
def V4_SA1_combine2i: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u2Imm:$u2),
"$Rdd = combine(#2, #$u2)"> {
bits<3> Rdd;
bits<2> u2;
let Inst{12-10} = 0b111;
let Inst{8} = 0b0;
let Inst{4-3} = 0b10;
let Inst{2-0} = Rdd;
let Inst{6-5} = u2;
}
// SA1_sxtb: Sxtb.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_sxtb: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = sxtb($Rs)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10101;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SA1_clrf: Clear if false.
// SA1_clrf -> SA1_clrfnew
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrf: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (!p0) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
let Inst{6-4} = 0b111;
let Inst{3-0} = Rd;
}
// SL2_loadrb_io: Load byte.
let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL2_loadrb_io: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs, u3_0Imm:$u3_0),
"$Rd = memb($Rs + #$u3_0)"> {
bits<4> Rd;
bits<4> Rs;
bits<3> u3_0;
let Inst{12-11} = 0b10;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
let Inst{10-8} = u3_0;
}
// SA1_tfr: Tfr.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_tfr: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = $Rs"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10000;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SL2_loadrd_sp: Load dword.
let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
def V4_SL2_loadrd_sp: SUBInst <
(outs DoubleRegs:$Rdd),
(ins u5_3Imm:$u5_3),
"$Rdd = memd(r29 + #$u5_3)"> {
bits<3> Rdd;
bits<8> u5_3;
let Inst{12-8} = 0b11110;
let Inst{2-0} = Rdd;
let Inst{7-3} = u5_3{7-3};
}
// SA1_and1: And #1.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_and1: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = and($Rs, #1)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10010;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SS2_storebi1: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
def V4_SS2_storebi1: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0),
"memb($Rs + #$u4_0)=#1"> {
bits<4> Rs;
bits<4> u4_0;
let Inst{12-8} = 0b10011;
let Inst{7-4} = Rs;
let Inst{3-0} = u4_0;
}
// SA1_inc: Inc.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_inc: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = add($Rs, #1)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10001;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SS2_stored_sp: Store dword.
let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in
def V4_SS2_stored_sp: SUBInst <
(outs ),
(ins s6_3Imm:$s6_3, DoubleRegs:$Rtt),
"memd(r29 + #$s6_3) = $Rtt"> {
bits<9> s6_3;
bits<3> Rtt;
let Inst{12-9} = 0b0101;
let Inst{8-3} = s6_3{8-3};
let Inst{2-0} = Rtt;
}
// SS2_storew_sp: Store word.
let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
def V4_SS2_storew_sp: SUBInst <
(outs ),
(ins u5_2Imm:$u5_2, IntRegs:$Rt),
"memw(r29 + #$u5_2) = $Rt"> {
bits<7> u5_2;
bits<4> Rt;
let Inst{12-9} = 0b0100;
let Inst{8-4} = u5_2{6-2};
let Inst{3-0} = Rt;
}
// SL2_jumpr31_fnew: Indirect conditional jump if false.
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
def V4_SL2_jumpr31_fnew: SUBInst <
(outs ),
(ins ),
"if (!p0.new) jumpr:nt r31"> {
let Inst{12-6} = 0b1111111;
let Inst{2-0} = 0b111;
}
// SA1_clrt: Clear if true.
// SA1_clrt -> SA1_clrtnew
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrt: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (p0) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
let Inst{6-4} = 0b110;
let Inst{3-0} = Rd;
}
// SL2_return: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
def V4_SL2_return: SUBInst <
(outs ),
(ins ),
"dealloc_return"> {
let Inst{12-6} = 0b1111101;
let Inst{2} = 0b0;
}
// SA1_dec: Dec.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_dec: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = add($Rs,#-1)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10011;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SA1_seti: Set immed.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in
def V4_SA1_seti: SUBInst <
(outs IntRegs:$Rd),
(ins u6Ext:$u6),
"$Rd = #$u6"> {
bits<4> Rd;
bits<6> u6;
let Inst{12-10} = 0b010;
let Inst{3-0} = Rd;
let Inst{9-4} = u6;
}
// SL2_jumpr31_t: Indirect conditional jump if true.
// SL2_jumpr31_t -> SL2_jumpr31_tnew
let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
def V4_SL2_jumpr31_t: SUBInst <
(outs ),
(ins ),
"if (p0) jumpr r31"> {
let Inst{12-6} = 0b1111111;
let Inst{2-0} = 0b100;
}
// SA1_clrfnew: Clear if false.
let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_clrfnew: SUBInst <
(outs IntRegs:$Rd),
(ins ),
"if (!p0.new) $Rd = #0"> {
bits<4> Rd;
let Inst{12-9} = 0b1101;
let Inst{6-4} = 0b101;
let Inst{3-0} = Rd;
}
// SS1_storew_io: Store word.
let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in
def V4_SS1_storew_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt),
"memw($Rs + #$u4_2) = $Rt"> {
bits<4> Rs;
bits<6> u4_2;
bits<4> Rt;
let Inst{12} = 0b0;
let Inst{7-4} = Rs;
let Inst{11-8} = u4_2{5-2};
let Inst{3-0} = Rt;
}
// SA1_zxtb: Zxtb.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_zxtb: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = and($Rs, #255)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10111;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}
// SA1_addsp: Add.
let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_addsp: SUBInst <
(outs IntRegs:$Rd),
(ins u6_2Imm:$u6_2),
"$Rd = add(r29, #$u6_2)"> {
bits<4> Rd;
bits<8> u6_2;
let Inst{12-10} = 0b011;
let Inst{3-0} = Rd;
let Inst{9-4} = u6_2{7-2};
}
// SL2_loadri_sp: Load word.
let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
def V4_SL2_loadri_sp: SUBInst <
(outs IntRegs:$Rd),
(ins u5_2Imm:$u5_2),
"$Rd = memw(r29 + #$u5_2)"> {
bits<4> Rd;
bits<7> u5_2;
let Inst{12-9} = 0b1110;
let Inst{3-0} = Rd;
let Inst{8-4} = u5_2{6-2};
}
// SS1_storeb_io: Store byte.
let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in
def V4_SS1_storeb_io: SUBInst <
(outs ),
(ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt),
"memb($Rs + #$u4_0) = $Rt"> {
bits<4> Rs;
bits<4> u4_0;
bits<4> Rt;
let Inst{12} = 0b1;
let Inst{7-4} = Rs;
let Inst{11-8} = u4_0;
let Inst{3-0} = Rt;
}
// SL2_return_tnew: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
def V4_SL2_return_tnew: SUBInst <
(outs ),
(ins ),
"if (p0.new) dealloc_return:nt"> {
let Inst{12-6} = 0b1111101;
let Inst{2-0} = 0b110;
}
// SL2_return_fnew: Deallocate stack frame and return.
let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in
def V4_SL2_return_fnew: SUBInst <
(outs ),
(ins ),
"if (!p0.new) dealloc_return:nt"> {
let Inst{12-6} = 0b1111101;
let Inst{2-0} = 0b111;
}
// SA1_zxth: Zxth.
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
def V4_SA1_zxth: SUBInst <
(outs IntRegs:$Rd),
(ins IntRegs:$Rs),
"$Rd = zxth($Rs)"> {
bits<4> Rd;
bits<4> Rs;
let Inst{12-8} = 0b10110;
let Inst{3-0} = Rd;
let Inst{7-4} = Rs;
}

8
lib/Target/Hexagon/HexagonOperands.td
View File

@ -27,6 +27,7 @@ let PrintMethod = "printImmOperand" in {
def s8Imm : Operand<i32>;
def s8Imm64 : Operand<i64>;
def s6Imm : Operand<i32>;
def s6_3Imm : Operand<i32>;
def s4Imm : Operand<i32>;
def s4_0Imm : Operand<i32>;
def s4_1Imm : Operand<i32>;
@ -51,8 +52,14 @@ let PrintMethod = "printImmOperand" in {
def u6_2Imm : Operand<i32>;
def u6_3Imm : Operand<i32>;
def u5Imm : Operand<i32>;
def u5_2Imm : Operand<i32>;
def u5_3Imm : Operand<i32>;
def u4Imm : Operand<i32>;
def u4_0Imm : Operand<i32>;
def u4_2Imm : Operand<i32>;
def u3Imm : Operand<i32>;
def u3_0Imm : Operand<i32>;
def u3_1Imm : Operand<i32>;
def u2Imm : Operand<i32>;
def u1Imm : Operand<i32>;
def n8Imm : Operand<i32>;
@ -444,6 +451,7 @@ let PrintMethod = "printExtOperand" in {
def s10Ext : Operand<i32>;
def s9Ext : Operand<i32>;
def s8Ext : Operand<i32>;
def s7Ext : Operand<i32>;
def s6Ext : Operand<i32>;
def s11_0Ext : Operand<i32>;
def s11_1Ext : Operand<i32>;

1
lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt
View File

@ -4,6 +4,7 @@ add_llvm_library(LLVMHexagonDesc
HexagonInstPrinter.cpp
HexagonMCAsmInfo.cpp
HexagonMCCodeEmitter.cpp
HexagonMCDuplexInfo.cpp
HexagonMCInstrInfo.cpp
HexagonMCShuffler.cpp
HexagonMCTargetDesc.cpp

1
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@ -16,6 +16,7 @@
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;

12
lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
View File

@ -43,6 +43,7 @@ namespace HexagonII {
TypeXTYPE = 8,
TypeMEMOP = 9,
TypeNV = 10,
TypeDUPLEX = 11,
TypePREFIX = 30, // Such as extenders.
TypeENDLOOP = 31 // Such as end of a HW loop.
};
@ -190,6 +191,17 @@ namespace HexagonII {
MO_GPREL
};
// Hexagon Sub-instruction classes.
enum SubInstructionGroup {
HSIG_None = 0,
HSIG_L1,
HSIG_L2,
HSIG_S1,
HSIG_S2,
HSIG_A,
HSIG_Compound
};
enum InstParseBits {
INST_PARSE_MASK = 0x0000c000,
INST_PARSE_PACKET_END = 0x0000c000,

8
lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp
View File

@ -129,7 +129,13 @@ void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &OS,
HasExtender = false;
for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) {
MCInst const &MCI = *I.getInst();
printInstruction(&MCI, OS);
if (HexagonMCInstrInfo::isDuplex(MII, MCI)) {
printInstruction(MCI.getOperand(1).getInst(), OS);
OS << '\v';
HasExtender = false;
printInstruction(MCI.getOperand(0).getInst(), OS);
} else
printInstruction(&MCI, OS);
setExtender(MCI);
OS << "\n";
}

82
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
View File

@ -40,18 +40,25 @@ HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
MCInst const &MCB,
MCInst const &MCI) const {
bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
if (Instruction == 0) {
if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
assert(!Duplex);
assert(Instruction != Last);
return HexagonII::INST_PARSE_LOOP_END;
}
}
if (Instruction == 1) {
if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
assert(!Duplex);
assert(Instruction != Last);
return HexagonII::INST_PARSE_LOOP_END;
}
}
if (Duplex) {
assert(Instruction == Last);
return HexagonII::INST_PARSE_DUPLEX;
}
if(Instruction == Last)
return HexagonII::INST_PARSE_PACKET_END;
return HexagonII::INST_PARSE_NOT_END;
@ -149,6 +156,81 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(
llvm_unreachable("Unimplemented Instruction");
}
Binary |= Parse;
// if we need to emit a duplexed instruction
if (HMB.getOpcode() >= Hexagon::DuplexIClass0 &&
HMB.getOpcode() <= Hexagon::DuplexIClassF) {
assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
"Emitting duplex without duplex parse bits");
unsigned dupIClass;
switch (HMB.getOpcode()) {
case Hexagon::DuplexIClass0:
dupIClass = 0;
break;
case Hexagon::DuplexIClass1:
dupIClass = 1;
break;
case Hexagon::DuplexIClass2:
dupIClass = 2;
break;
case Hexagon::DuplexIClass3:
dupIClass = 3;
break;
case Hexagon::DuplexIClass4:
dupIClass = 4;
break;
case Hexagon::DuplexIClass5:
dupIClass = 5;
break;
case Hexagon::DuplexIClass6:
dupIClass = 6;
break;
case Hexagon::DuplexIClass7:
dupIClass = 7;
break;
case Hexagon::DuplexIClass8:
dupIClass = 8;
break;
case Hexagon::DuplexIClass9:
dupIClass = 9;
break;
case Hexagon::DuplexIClassA:
dupIClass = 10;
break;
case Hexagon::DuplexIClassB:
dupIClass = 11;
break;
case Hexagon::DuplexIClassC:
dupIClass = 12;
break;
case Hexagon::DuplexIClassD:
dupIClass = 13;
break;
case Hexagon::DuplexIClassE:
dupIClass = 14;
break;
case Hexagon::DuplexIClassF:
dupIClass = 15;
break;
default:
llvm_unreachable("Unimplemented DuplexIClass");
break;
}
// 29 is the bit position.
// 0b1110 =0xE bits are masked off and down shifted by 1 bit.
// Last bit is moved to bit position 13
Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
const MCInst *subInst0 = HMB.getOperand(0).getInst();
const MCInst *subInst1 = HMB.getOperand(1).getInst();
// get subinstruction slot 0
unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
// get subinstruction slot 1
unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
}
support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
++MCNumEmitted;
}

1100
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp Normal file
View File

File diff suppressed because it is too large Load Diff

68
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
View File

@ -16,6 +16,8 @@
#include "Hexagon.h"
#include "HexagonBaseInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
namespace llvm {
@ -33,6 +35,32 @@ size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
return (1);
}
MCInst *HexagonMCInstrInfo::deriveDuplex(MCContext &Context, unsigned iClass,
MCInst const &inst0,
MCInst const &inst1) {
assert((iClass <= 0xf) && "iClass must have range of 0 to 0xf");
MCInst *duplexInst = new (Context) MCInst;
duplexInst->setOpcode(Hexagon::DuplexIClass0 + iClass);
MCInst *SubInst0 = new (Context) MCInst(deriveSubInst(inst0));
MCInst *SubInst1 = new (Context) MCInst(deriveSubInst(inst1));
duplexInst->addOperand(MCOperand::createInst(SubInst0));
duplexInst->addOperand(MCOperand::createInst(SubInst1));
return duplexInst;
}
MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
size_t Index) {
assert(Index <= bundleSize(MCB));
if (Index == 0)
return nullptr;
MCInst const *Inst =
MCB.getOperand(Index + bundleInstructionsOffset - 1).getInst();
if (isImmext(*Inst))
return Inst;
return nullptr;
}
HexagonII::MemAccessSize
HexagonMCInstrInfo::getAccessSize(MCInstrInfo const &MCII, MCInst const &MCI) {
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
@ -188,6 +216,10 @@ bool HexagonMCInstrInfo::hasImmExt(MCInst const &MCI) {
return false;
}
bool HexagonMCInstrInfo::hasExtenderForIndex(MCInst const &MCB, size_t Index) {
return extenderForIndex(MCB, Index) != nullptr;
}
// Return whether the instruction is a legal new-value producer.
bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
MCInst const &MCI) {
@ -214,6 +246,15 @@ bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
HexagonMCInstrInfo::getType(MCII, MCI) != HexagonII::TypeENDLOOP);
}
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
(Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
}
bool HexagonMCInstrInfo::isDuplex(MCInstrInfo const &MCII, MCInst const &MCI) {
return HexagonII::TypeDUPLEX == HexagonMCInstrInfo::getType(MCII, MCI);
}
// Return whether the instruction needs to be constant extended.
// 1) Always return true if the instruction has 'isExtended' flag set.
//
@ -281,6 +322,15 @@ bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
return (Flags & innerLoopMask) != 0;
}
bool HexagonMCInstrInfo::isIntReg(unsigned Reg) {
return (Reg >= Hexagon::R0 && Reg <= Hexagon::R31);
}
bool HexagonMCInstrInfo::isIntRegForSubInst(unsigned Reg) {
return ((Reg >= Hexagon::R0 && Reg <= Hexagon::R7) ||
(Reg >= Hexagon::R16 && Reg <= Hexagon::R23));
}
// Return whether the insn is a new-value consumer.
bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
MCInst const &MCI) {
@ -316,6 +366,10 @@ bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
!((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
}
bool HexagonMCInstrInfo::isPredReg(unsigned Reg) {
return (Reg >= Hexagon::P0 && Reg <= Hexagon::P3_0);
}
bool HexagonMCInstrInfo::isPrefix(MCInstrInfo const &MCII, MCInst const &MCI) {
return (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypePREFIX);
}
@ -367,6 +421,20 @@ bool HexagonMCInstrInfo::prefersSlot3(MCInstrInfo const &MCII,
return false;
}
void HexagonMCInstrInfo::replaceDuplex(MCContext &Context, MCInst &MCB,
DuplexCandidate Candidate) {
assert(Candidate.packetIndexI < MCB.size());
assert(Candidate.packetIndexJ < MCB.size());
assert(isBundle(MCB));
MCInst *Duplex =
deriveDuplex(Context, Candidate.iClass,
*MCB.getOperand(Candidate.packetIndexJ).getInst(),
*MCB.getOperand(Candidate.packetIndexI).getInst());
assert(Duplex != nullptr);
MCB.getOperand(Candidate.packetIndexI).setInst(Duplex);
MCB.erase(MCB.begin() + Candidate.packetIndexJ);
}
void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
assert(isBundle(MCI));
MCOperand &Operand = MCI.getOperand(0);

60
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h
View File

@ -15,15 +15,14 @@
#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrInfo.h"
#include <bitset>
namespace llvm {
class MCContext;
class MCInstrDesc;
class MCInstrInfo;
class MCInst;
class MCOperand;
class MCSubtargetInfo;
namespace HexagonII {
enum class MemAccessSize;
}
@ -48,6 +47,16 @@ size_t bundleSize(MCInst const &MCI);
// Returns a iterator range of instructions in this bundle
iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
// Return the extender for instruction at Index or nullptr if none
MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
// Create a duplex instruction given the two subinsts
MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
MCInst const &inst1);
// Convert this instruction in to a duplex subinst
MCInst deriveSubInst(MCInst const &Inst);
// Return memory access size
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
MCInst const &MCI);
@ -60,6 +69,13 @@ unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
// Return which duplex group this instruction belongs to
unsigned getDuplexCandidateGroup(MCInst const &MI);
// Return a list of all possible instruction duplex combinations
SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII,
MCInst const &MCB);
// Return the index of the extendable operand
unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
@ -99,6 +115,9 @@ unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
MCInst const &MCI);
// Does the packet have an extender for the instruction at Index
bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
bool hasImmExt(MCInst const &MCI);
// Return whether the instruction is a legal new-value producer.
@ -113,9 +132,24 @@ bool isBundle(MCInst const &MCI);
// Return whether the insn is an actual insn.
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
// Return the duplex iclass given the two duplex classes
unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
// Return whether the instruction needs to be constant extended.
bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
// Is this double register suitable for use in a duplex subinst
bool isDblRegForSubInst(unsigned Reg);
// Is this a duplex instruction
bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
// Can these instructions be duplexed
bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
// Can these duplex classes be combine in to a duplex instruction
bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
// Return true if the insn may be extended based on the operand value.
bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
@ -131,6 +165,12 @@ bool isImmext(MCInst const &MCI);
// Returns whether this bundle is an endloop0
bool isInnerLoop(MCInst const &MCI);
// Is this an integer register
bool isIntReg(unsigned Reg);
// Is this register suitable for use in a duplex subinst
bool isIntRegForSubInst(unsigned Reg);
// Return whether the insn is a new-value consumer.
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
@ -138,6 +178,11 @@ bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI,
unsigned short OperandNum);
// Can these two instructions be duplexed
bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
bool ExtendedA, MCInst const &MIb, bool ExtendedB,
bool bisReversable);
// Returns whether this bundle is an endloop1
bool isOuterLoop(MCInst const &MCI);
@ -147,6 +192,9 @@ bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
// Return whether the predicate sense is true
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
// Is this a predicate register
bool isPredReg(unsigned Reg);
// Return whether the insn is a prefix.
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
@ -164,11 +212,17 @@ void padEndloop(MCInst &MCI);
bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
// Replace the instructions inside MCB, represented by Candidate
void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate);
// Marks a bundle as endloop0
void setInnerLoop(MCInst &MCI);
// Marks a bundle as endloop1
void setOuterLoop(MCInst &MCI);
// Would duplexing this instruction create a requirement to extend
bool subInstWouldBeExtended(MCInst const &potentialDuplex);
}
}

55
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp
View File

@ -147,6 +147,61 @@ bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
return true;
}
unsigned
llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
MCContext &Context, MCInst &MCB,
SmallVector<DuplexCandidate, 8> possibleDuplexes) {
if (DisableShuffle)
return HexagonShuffler::SHUFFLE_SUCCESS;
if (!HexagonMCInstrInfo::bundleSize(MCB)) {
// There once was a bundle:
// BUNDLE %D2<imp-def>, %R4<imp-def>, %R5<imp-def>, %D7<imp-def>, ...
// * %D2<def> = IMPLICIT_DEF; flags:
// * %D7<def> = IMPLICIT_DEF; flags:
// After the IMPLICIT_DEFs were removed by the asm printer, the bundle
// became empty.
DEBUG(dbgs() << "Skipping empty bundle");
return HexagonShuffler::SHUFFLE_SUCCESS;
} else if (!HexagonMCInstrInfo::isBundle(MCB)) {
DEBUG(dbgs() << "Skipping stand-alone insn");
return HexagonShuffler::SHUFFLE_SUCCESS;
}
bool doneShuffling = false;
unsigned shuffleError;
while (possibleDuplexes.size() > 0 && (!doneShuffling)) {
// case of Duplex Found
DuplexCandidate duplexToTry = possibleDuplexes.pop_back_val();
MCInst Attempt(MCB);
HexagonMCInstrInfo::replaceDuplex(Context, Attempt, duplexToTry);
HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler
if (MCS.size() == 1) { // case of one duplex
// copy the created duplex in the shuffler to the bundle
MCS.copyTo(MCB);
doneShuffling = true;
return HexagonShuffler::SHUFFLE_SUCCESS;
}
// try shuffle with this duplex
doneShuffling = MCS.reshuffleTo(MCB);
shuffleError = MCS.getError();
if (doneShuffling)
break;
}
if (doneShuffling == false) {
HexagonMCShuffler MCS(MCII, STI, MCB);
doneShuffling = MCS.reshuffleTo(MCB); // shuffle
shuffleError = MCS.getError();
}
if (!doneShuffling)
return shuffleError;
return HexagonShuffler::SHUFFLE_SUCCESS;
}
bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
MCInst &MCB, MCInst const *AddMI, int fixupCount) {
if (!HexagonMCInstrInfo::isBundle(MCB) || !AddMI)

8
test/CodeGen/Hexagon/args.ll
View File

@ -1,8 +1,8 @@
; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
; CHECK: r1:0 = combine(#2, #1)
; CHECK: r3:2 = combine(#4, #3)
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r5:4 = combine(#6, #5)
; CHECK: r3:2 = combine(#4, #3)
; CHECK: r1:0 = combine(#2, #1)
; CHECK: memw(r29{{ *}}+{{ *}}#0){{ *}}={{ *}}#7
define void @foo() nounwind {

73
test/CodeGen/Hexagon/calling-conv.ll
View File

@ -1,73 +0,0 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
; RUN: FileCheck %s --check-prefix=CHECK-ONE
; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
; RUN: FileCheck %s --check-prefix=CHECK-TWO
; RUN: llc -march=hexagon -mcpu=hexagonv5 <%s | \
; RUN: FileCheck %s --check-prefix=CHECK-THREE
%struct.test_struct = type { i32, i8, i64 }
%struct.test_struct_long = type { i8, i64 }
@mystruct = external global %struct.test_struct*, align 4
; CHECK-ONE: memw(r29+#48) = r2
; CHECK-TWO: memw(r29+#52) = r2
; CHECK-THREE: memw(r29+#56) = r2
; Function Attrs: nounwind
define void @foo(%struct.test_struct* noalias sret %agg.result, i32 %a, i8 zeroext %c, %struct.test_struct* byval %s, %struct.test_struct_long* byval %t) #0 {
entry:
%a.addr = alloca i32, align 4
%c.addr = alloca i8, align 1
%z = alloca i32, align 4
%ret = alloca %struct.test_struct, align 8
store i32 %a, i32* %a.addr, align 4
store i8 %c, i8* %c.addr, align 1
%0 = bitcast i32* %z to i8*
call void @llvm.lifetime.start(i64 4, i8* %0) #1
store i32 45, i32* %z, align 4
%1 = bitcast %struct.test_struct* %ret to i8*
call void @llvm.lifetime.start(i64 16, i8* %1) #1
%2 = load i32, i32* %z, align 4
%3 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
%4 = load %struct.test_struct*, %struct.test_struct** @mystruct, align 4
%5 = load i8, i8* %c.addr, align 1
%6 = load i32, i32* %a.addr, align 4
%conv = sext i32 %6 to i64
%add = add nsw i64 %conv, 1
%7 = load i32, i32* %a.addr, align 4
%add1 = add nsw i32 %7, 2
%8 = load i32, i32* %a.addr, align 4
%conv2 = sext i32 %8 to i64
%add3 = add nsw i64 %conv2, 3
%9 = load i8, i8* %c.addr, align 1
%10 = load i8, i8* %c.addr, align 1
%11 = load i8, i8* %c.addr, align 1
%12 = load i32, i32* %z, align 4
call void @bar(%struct.test_struct* sret %ret, i32 %2, %struct.test_struct* byval %3, %struct.test_struct* byval %4, i8 zeroext %5, i64 %add, i32 %add1, i64 %add3, i8 zeroext %9, i8 zeroext %10, i8 zeroext %11, i32 %12)
%x = getelementptr inbounds %struct.test_struct, %struct.test_struct* %ret, i32 0, i32 0
store i32 20, i32* %x, align 4
%13 = bitcast %struct.test_struct* %agg.result to i8*
%14 = bitcast %struct.test_struct* %ret to i8*
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %13, i8* %14, i32 16, i32 8, i1 false)
%15 = bitcast %struct.test_struct* %ret to i8*
call void @llvm.lifetime.end(i64 16, i8* %15) #1
%16 = bitcast i32* %z to i8*
call void @llvm.lifetime.end(i64 4, i8* %16) #1
ret void
}
; Function Attrs: nounwind
declare void @llvm.lifetime.start(i64, i8* nocapture) #1
declare void @bar(%struct.test_struct* sret, i32, %struct.test_struct* byval, %struct.test_struct* byval, i8 zeroext, i64, i32, i64, i8 zeroext, i8 zeroext, i8 zeroext, i32) #2
; Function Attrs: nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1
; Function Attrs: nounwind
declare void @llvm.lifetime.end(i64, i8* nocapture) #1
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind }
attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv4" "unsafe-fp-math"="false" "use-soft-float"="false" }

15
test/CodeGen/Hexagon/dualstore.ll
View File

@ -1,12 +1,11 @@
; RUN: llc -march=hexagon -disable-hexagon-misched < %s | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
; Check that we generate dual stores in one packet in V4
; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
; CHECK-NEXT: memw(r{{[0-9]+}}{{ *}}+{{ *}}#{{[0-9]+}}){{ *}}=
; CHECK: 00 40 9f 52 529f4000
; CHECK: 10 10 00 f0 f0001010
define i32 @main(i32 %v, i32* %p1, i32* %p2) nounwind {
entry:
store i32 %v, i32* %p1, align 4
store i32 %v, i32* %p2, align 4
ret i32 0
define void @foo(i32* %a, i32* %b) {
store i32 0, i32* %a
store i32 0, i32* %b
ret void
}

7
test/CodeGen/Hexagon/duplex.ll Normal file
View File

@ -0,0 +1,7 @@
; RUN: llc -march=hexagon -filetype=obj -o - %s | llvm-objdump -d - | FileCheck %s
; CHECK: c0 3f 00 48 48003fc0
define i32 @foo() {
ret i32 0
}

4
test/CodeGen/Hexagon/sube.ll
View File

@ -3,10 +3,10 @@
; CHECK: r{{[0-9]+:[0-9]+}} = #1
; CHECK: r{{[0-9]+:[0-9]+}} = #0
; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}})
; CHECK: r{{[0-9]+:[0-9]+}} = combine(r{{[0-9]+}}, r{{[0-9]+}})
define void @check_sube_subc(i64 %AL, i64 %AH, i64 %BL, i64 %BH, i64* %RL, i64* %RH) {

6
test/MC/Hexagon/inst_add.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i32 %a, i32 %b)
{
@ -7,4 +7,4 @@ define i32 @foo (i32 %a, i32 %b)
ret i32 %1
}
; CHECK: 0000 004100f3 00c09f52
; CHECK: c0 3f 10 58 58103fc0

9
test/MC/Hexagon/inst_select.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i1 %a, i32 %b, i32 %c)
{
@ -7,4 +7,7 @@ define i32 @foo (i1 %a, i32 %b, i32 %c)
ret i32 %1
}
; CHECK: 0000 00400085 00600174 00608274 00c09f52
; CHECK: 00 40 00 85 85004000
; CHECK: 00 40 9f 52 529f4000
; CHECK: 00 60 01 74 74016000
; CHECK: 00 e0 82 74 7482e000

6
test/MC/Hexagon/inst_sxtb.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i8 %a)
{
@ -7,4 +7,4 @@ define i32 @foo (i8 %a)
ret i32 %1
}
; CHECK: 0000 0040a070 00c09f52
; CHECK: c0 3f 00 55 55003fc0

6
test/MC/Hexagon/inst_sxth.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i16 %a)
{
@ -7,4 +7,4 @@ define i32 @foo (i16 %a)
ret i32 %1
}
; CHECK: 0000 0040e070 00c09f52
; CHECK: c0 3f 00 54 54003fc0

6
test/MC/Hexagon/inst_zxtb.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i8 %a)
{
@ -7,4 +7,4 @@ define i32 @foo (i8 %a)
ret i32 %1
}
; CHECK: 0000 e05f0076 00c09f52
; CHECK: c0 3f 00 57 57003fc0

6
test/MC/Hexagon/inst_zxth.ll
View File

@ -1,5 +1,5 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s
; RUN: llc -march=hexagon -filetype=obj %s -o - \
; RUN: | llvm-objdump -d - | FileCheck %s
define i32 @foo (i16 %a)
{
@ -7,4 +7,4 @@ define i32 @foo (i16 %a)
ret i32 %1
}
; CHECK: 0000 0040c070 00c09f52
; CHECK: c0 3f 00 56 56003fc0