From 750dbd5950ab5a6689f189adbea900eee9e6884d Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 15 Oct 2005 22:35:40 +0000 Subject: [PATCH] Fix this logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23756 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 35c981d7f3d..5b1d10335cf 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -808,7 +808,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) { if (ConstantSDNode *N01C = dyn_cast(N0.getOperand(1))) { // If the RHS of the AND has zeros where the sign bits of the SRA will // land, turn the SRA into an SRL. - if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) & + if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & (~0ULL>>(64-OpSizeInBits)), TLI)) { WorkList.push_back(N); CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),