6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-05 13:26:55 +00:00
Code Issues Projects Releases Wiki Activity

Hexagon V5 FP Support.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sirish Pande
2012-05-10 20:20:25 +00:00
parent 55ba5dff3c
commit 7517bbc91a
29 changed files with 871 additions and 203 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
test/CodeGen/Hexagon/fadd.ll Normal file
View File

@@ -0,0 +1,18 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
; Check that we generate sp floating point add in V5.
; CHECK: r{{[0-9]+}} = sfadd(r{{[0-9]+}}, r{{[0-9]+}})
define i32 @main() nounwind {
entry:
%a = alloca float, align 4
%b = alloca float, align 4
%c = alloca float, align 4
store float 0x402ECCCCC0000000, float* %a, align 4
store float 0x4022333340000000, float* %b, align 4
%0 = load float* %a, align 4
%1 = load float* %b, align 4
%add = fadd float %0, %1
store float %add, float* %c, align 4
ret i32 0
}