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Fix that pesky floats in integer regs problem by assigning the f32 type to

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the correct register class.  Also remove the loading of float data into int
regs part of varargs; it will need to be implemented differently later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20857 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-03-26 08:25:22 +00:00
parent f7e4338035
commit 7532e2f555
1 changed files with 4 additions and 8 deletions
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12
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -44,7 +44,7 @@ namespace {
// Set up the register classes.
addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
computeRegisterProperties();
@ -322,13 +322,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
// store only the non-fixed arguments in a vararg function.
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
Args[i].first, PtrOff));
if (GPR_remaining > 0)
args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
if (GPR_remaining > 1) {
SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
args_to_use.push_back(DAG.getLoad(MVT::i32, Chain, PtrOff));
}
// FIXME: Need a way to communicate to the ISD::CALL select code
// that a particular argument is non-fixed so that we can load them
// into the correct GPR to shadow the FPR
}
args_to_use.push_back(Args[i].first);
--FPR_remaining;