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AArch64/ARM64: add non-scalar lowering for more FCVT operations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-04-18 13:16:42 +00:00
parent 7b4b522ec8
commit 753cfe6172
3 changed files with 1913 additions and 2 deletions
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10
lib/Target/ARM64/ARM64ISelLowering.cpp
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@ -1313,10 +1313,16 @@ static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
if (VT.getSizeInBits() == InVT.getSizeInBits())
return Op;
if (InVT == MVT::v2f64) {
if (InVT == MVT::v2f64 || InVT == MVT::v4f32) {
SDLoc dl(Op);
SDValue Cv = DAG.getNode(Op.getOpcode(), dl, MVT::v2i64, Op.getOperand(0));
SDValue Cv =
DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(),
Op.getOperand(0));
return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv);
} else if (InVT == MVT::v2f32) {
SDLoc dl(Op);
SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, Op.getOperand(0));
return DAG.getNode(Op.getOpcode(), dl, VT, Ext);
}
// Type changing conversions are illegal.

4
lib/Target/ARM64/ARM64TargetTransformInfo.cpp
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@ -316,6 +316,10 @@ unsigned ARM64TTI::getCastInstrCost(unsigned Opcode, Type *Dst,
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 1 },
{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f32, 4 },
{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 4 },
{ ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 4 },
{ ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 4 },
{ ISD::FP_TO_UINT, MVT::v2i64, MVT::v2f64, 4 },
{ ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 4 },
};

1901
test/CodeGen/ARM64/aarch64-neon-misc.ll Normal file
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