mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-09 16:45:03 +00:00
[Hexagon] Adding some compare tests, fixing existing XFAILed tests, and removing mcpu=hexagonv4 since that's the minimum version anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239917 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
d562b72225
commit
7540f2c60a
40
test/CodeGen/Hexagon/cmp-extend.ll
Normal file
40
test/CodeGen/Hexagon/cmp-extend.ll
Normal file
@ -0,0 +1,40 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
|
||||
%struct.RESULTS_S.A = type { i16, i16, i16, [4 x i8*], i32, i32, i32, %struct.list_head_s.B*, %struct.MAT_PARAMS_S.D, i16, i16, i16, i16, i16, %struct.CORE_PORTABLE_S.E }
|
||||
%struct.list_head_s.B = type { %struct.list_head_s.B*, %struct.list_data_s.C* }
|
||||
%struct.list_data_s.C = type { i16, i16 }
|
||||
%struct.MAT_PARAMS_S.D = type { i32, i16*, i16*, i32* }
|
||||
%struct.CORE_PORTABLE_S.E = type { i8 }
|
||||
|
||||
; Test that we don't generate a zero extend in this case. Instead we generate
|
||||
; a single sign extend instead of two zero extends.
|
||||
|
||||
; CHECK-NOT: zxth
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define void @core_bench_list(%struct.RESULTS_S.A* %res) #0 {
|
||||
entry:
|
||||
%seed3 = getelementptr inbounds %struct.RESULTS_S.A, %struct.RESULTS_S.A* %res, i32 0, i32 2
|
||||
%0 = load i16, i16* %seed3, align 2
|
||||
%cmp364 = icmp sgt i16 %0, 0
|
||||
br i1 %cmp364, label %for.body, label %while.body19.i160
|
||||
|
||||
for.body:
|
||||
%i.0370 = phi i16 [ %inc50, %if.then ], [ 0, %entry ]
|
||||
br i1 undef, label %if.then, label %while.body.i273
|
||||
|
||||
while.body.i273:
|
||||
%tobool.i272 = icmp eq %struct.list_head_s.B* undef, null
|
||||
br i1 %tobool.i272, label %if.then, label %while.body.i273
|
||||
|
||||
if.then:
|
||||
%inc50 = add i16 %i.0370, 1
|
||||
%exitcond = icmp eq i16 %inc50, %0
|
||||
br i1 %exitcond, label %while.body19.i160, label %for.body
|
||||
|
||||
while.body19.i160:
|
||||
br label %while.body19.i160
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
|
||||
72
test/CodeGen/Hexagon/cmp-promote.ll
Normal file
72
test/CodeGen/Hexagon/cmp-promote.ll
Normal file
@ -0,0 +1,72 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
;
|
||||
; Bug 6714. Use sign-extend to promote the arguments for compare
|
||||
; equal/not-equal for 8- and 16-bit types with negative constants.
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-16
|
||||
define i32 @foo1(i16 signext %q) nounwind readnone {
|
||||
entry:
|
||||
%not.cmp = icmp ne i16 %q, -16
|
||||
%res.0 = zext i1 %not.cmp to i32
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-14
|
||||
define i32 @foo2(i16 signext %q) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i16 %q, -14
|
||||
%res.0 = select i1 %cmp, i32 2, i32 0
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-8
|
||||
define i32 @foo3(i8 signext %r) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i8 %r, -8
|
||||
%res.0 = select i1 %cmp, i32 0, i32 3
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-6
|
||||
define i32 @foo4(i8 signext %r) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i8 %r, -6
|
||||
%res.0 = select i1 %cmp, i32 4, i32 0
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-20
|
||||
define i32 @foo5(i32 %s) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i32 %s, -20
|
||||
%res.0 = select i1 %cmp, i32 0, i32 5
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-18
|
||||
define i32 @foo6(i32 %s) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i32 %s, -18
|
||||
%res.0 = select i1 %cmp, i32 6, i32 0
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#10
|
||||
define i32 @foo7(i16 signext %q) nounwind readnone {
|
||||
entry:
|
||||
%cmp = icmp eq i16 %q, 10
|
||||
%res.0 = select i1 %cmp, i32 7, i32 0
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
@g = external global i16
|
||||
|
||||
; CHECK: cmp.eq{{.*}}#-12
|
||||
define i32 @foo8() nounwind readonly {
|
||||
entry:
|
||||
%0 = load i16, i16* @g, align 2
|
||||
%cmp = icmp eq i16 %0, -12
|
||||
%res.0 = select i1 %cmp, i32 0, i32 8
|
||||
ret i32 %res.0
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
; Check that we generate compare to general register.
|
||||
|
||||
define i32 @compare1(i32 %a) nounwind {
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
; Check that we generate compare to predicate register.
|
||||
|
||||
define i32 @compare1(i32 %a, i32 %b) nounwind {
|
||||
|
||||
161
test/CodeGen/Hexagon/cmp.ll
Normal file
161
test/CodeGen/Hexagon/cmp.ll
Normal file
@ -0,0 +1,161 @@
|
||||
; RUN: llc -march=hexagon --filetype=obj < %s -o - | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpeq(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpeq(i32 %0, i32 1)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpeq(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgt(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgt(i32 %0, i32 2)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgt(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgtu(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgtu(i32 %0, i32 3)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgtu(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmplt(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmplt(i32 %0, i32 4)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmplt(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpltu(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpltu(i32 %0, i32 5)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpltu(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpeqi(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpeqi(i32 %0, i32 10)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, {{.*}}#10)
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpeqi(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgti(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgti(i32 %0, i32 20)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#20)
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgti(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgtui(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgtui(i32 %0, i32 40)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#40)
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgtui(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgei(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgei(i32 %0, i32 3)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gt(r{{[0-9]}}, {{.*}}#2)
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgei(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgeu(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 3)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.gtu(r{{[0-9]}}, {{.*}}#2)
|
||||
|
||||
; Function Attrs: nounwind readnone
|
||||
declare i32 @llvm.hexagon.C2.cmpgeui(i32, i32) #1
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define i32 @cmpgeu0(i32 %i) #0 {
|
||||
entry:
|
||||
%i.addr = alloca i32, align 4
|
||||
store i32 %i, i32* %i.addr, align 4
|
||||
%0 = load i32, i32* %i.addr, align 4
|
||||
%1 = call i32 @llvm.hexagon.C2.cmpgeui(i32 %0, i32 0)
|
||||
ret i32 %1
|
||||
}
|
||||
; CHECK: { p{{[0-3]}} = cmp.eq(r{{[0-9]}}, r{{[0-9]}})
|
||||
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
attributes #1 = { nounwind readnone }
|
||||
|
||||
!llvm.ident = !{!0}
|
||||
|
||||
!0 = !{!"Clang 3.1"}
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
; XFAIL:
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
|
||||
target triple = "hexagon"
|
||||
@ -61,7 +60,7 @@ entry:
|
||||
|
||||
define i32 @Func_3gt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: mux
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp sgt i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
; XFAIL:
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
|
||||
target triple = "hexagon"
|
||||
@ -61,7 +60,7 @@ entry:
|
||||
|
||||
define i32 @Func_3gt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: mux
|
||||
; CHECK-NOT: mux
|
||||
%cmp = icmp sgt i32 %Enum_Par_Val, %pv2
|
||||
%selv = zext i1 %cmp to i32
|
||||
ret i32 %selv
|
||||
|
||||
53
test/CodeGen/Hexagon/cmpb-eq.ll
Normal file
53
test/CodeGen/Hexagon/cmpb-eq.ll
Normal file
@ -0,0 +1,53 @@
|
||||
; RUN: llc -march=hexagon < %s | FileCheck %s
|
||||
; CHECK-NOT: cmpb.eq(r{{[0-9]+}}, #-1)
|
||||
|
||||
target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"
|
||||
target triple = "hexagon"
|
||||
|
||||
%struct.wms_address_s = type { i32, i32, i32, i32, i8, [48 x i8] }
|
||||
|
||||
define zeroext i8 @qmi_wmsi_bin_to_addr(i8* %str, i8 zeroext %len, %struct.wms_address_s* %addr) nounwind optsize {
|
||||
entry:
|
||||
%cmp = icmp eq i8* %str, null
|
||||
%cmp2 = icmp eq %struct.wms_address_s* %addr, null
|
||||
%or.cond = or i1 %cmp, %cmp2
|
||||
br i1 %or.cond, label %if.then12, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
%dec = add i8 %len, -1
|
||||
%cmp3 = icmp ugt i8 %dec, 24
|
||||
%tobool27 = icmp eq i8 %dec, 0
|
||||
%or.cond31 = or i1 %cmp3, %tobool27
|
||||
br i1 %or.cond31, label %if.then12, label %for.body.lr.ph
|
||||
|
||||
for.body.lr.ph: ; preds = %if.then
|
||||
%dec626 = add i8 %len, -2
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %for.body.lr.ph, %if.end21
|
||||
%indvars.iv = phi i32 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %if.end21 ]
|
||||
%dec630 = phi i8 [ %dec626, %for.body.lr.ph ], [ %dec6, %if.end21 ]
|
||||
%str.pn = phi i8* [ %str, %for.body.lr.ph ], [ %str.addr.029, %if.end21 ]
|
||||
%str.addr.029 = getelementptr inbounds i8, i8* %str.pn, i32 1
|
||||
%0 = load i8, i8* %str.addr.029, align 1, !tbaa !0
|
||||
%cmp10 = icmp ugt i8 %0, -49
|
||||
br i1 %cmp10, label %if.then12.loopexit, label %if.end21
|
||||
|
||||
if.then12.loopexit: ; preds = %if.end21, %for.body
|
||||
br label %if.then12
|
||||
|
||||
if.then12: ; preds = %if.then12.loopexit, %if.then, %entry
|
||||
ret i8 0
|
||||
|
||||
if.end21: ; preds = %for.body
|
||||
%shr24 = lshr i8 %0, 4
|
||||
%arrayidx = getelementptr inbounds %struct.wms_address_s, %struct.wms_address_s* %addr, i32 0, i32 5, i32 %indvars.iv
|
||||
store i8 %shr24, i8* %arrayidx, align 1, !tbaa !0
|
||||
%dec6 = add i8 %dec630, -1
|
||||
%tobool = icmp eq i8 %dec630, 0
|
||||
%indvars.iv.next = add i32 %indvars.iv, 1
|
||||
br i1 %tobool, label %if.then12.loopexit, label %for.body
|
||||
}
|
||||
|
||||
!0 = !{!"omnipotent char", !1}
|
||||
!1 = !{!"Simple C/C++ TBAA"}
|
||||
@ -1,4 +1,3 @@
|
||||
; XFAIL:
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
|
||||
; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
|
||||
target triple = "hexagon"
|
||||
@ -64,7 +63,7 @@ entry:
|
||||
|
||||
define i32 @Func_3g(i32) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: mux
|
||||
; CHECK-NOT: mux
|
||||
%conv = and i32 %0, 255
|
||||
%cmp = icmp ult i32 %conv, 3
|
||||
%selv = zext i1 %cmp to i32
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user