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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75981 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -587,7 +587,6 @@ def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
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"sllg\t{$dst, $src, $amt}",
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"sllg\t{$dst, $src, $amt}",
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[(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
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[(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
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let Defs = [PSW] in {
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let Defs = [PSW] in {
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let isTwoAddress = 1 in
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let isTwoAddress = 1 in
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def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
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def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
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@ -604,6 +603,17 @@ def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
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(implicit PSW)]>;
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(implicit PSW)]>;
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} // Defs = [PSW]
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} // Defs = [PSW]
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let isTwoAddress = 1 in
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def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
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"rll\t{$src, $amt}",
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[(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
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def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
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"rllg\t{$dst, $src, $amt}",
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[(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
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def ROTL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
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"rllg\t{$dst, $src, $amt}",
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[(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Test instructions (like AND but do not produce any result
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// Test instructions (like AND but do not produce any result
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13
test/CodeGen/SystemZ/2009-06-02-Rotate.ll
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13
test/CodeGen/SystemZ/2009-06-02-Rotate.ll
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@ -0,0 +1,13 @@
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; RUN: llvm-as < %s | llc -march=systemz | grep rll
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target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-a0:16:16"
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target triple = "s390x-linux"
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define i32 @rotl(i32 %x, i32 %y, i32 %z) nounwind readnone {
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entry:
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%shl = shl i32 %x, 0 ; <i32> [#uses=1]
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%sub = sub i32 32, 0 ; <i32> [#uses=1]
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%shr = lshr i32 %x, %sub ; <i32> [#uses=1]
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%or = or i32 %shr, %shl ; <i32> [#uses=1]
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ret i32 %or
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}
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